Low-power digital VLSI approaches

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Abstract

This tutorial presents system level design approaches for implementation of high-performance and low-power DSP systems. The emphasis is on tradeoffs with respect to area, power and speed using design approaches ranging from algorithm level to architecture level to implementation levels. The topics covered include transformation techniques like pipelining, parallel processing, sub-expression sharing, retiming, and number splitting. Experimental results on power consumption using different implementation styles like carry-save and redundant arithmetic are presented. A novel cell replacement transformation is also presented which results in reduction of power consumption in multipliers by a factor of 15.

Original languageEnglish (US)
Pages (from-to)3-22
Number of pages20
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - Jan 1 1997

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Low-power digital VLSI approaches. / Parhi, Keshab K.

In: Proceedings - IEEE International Symposium on Circuits and Systems, 01.01.1997, p. 3-22.

Research output: Contribution to journalArticle

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