Low-power digit-serial multipliers

Yun Nan Chang, Janardhan H. Satyanarayana, Keshab K Parhi

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

Digit-serial implementation styles are best suited for implementation of digital signal processing systems which require moderate sampling rates. Digit-serial multipliers obtained using traditional unfolding techniques cannot be pipelined beyond a certain level because of the presence of feedback loops. In this paper, an alternative approach for the design of digit-serial multipliers is presented based on a novel cell replacement transformation. This transformation permits bit-level pipelining of the digit-serial multipliers thereby achieving sample speeds close to corresponding bit-parallel multipliers with significantly lower area. This increased sample speed can be traded with reduction in power supply voltage resulting in significant reduction in power consumption. The results show that for smaller digit-sizes (≤4), the type-II multiplier consumes the least power and for larger digit-sizes, the type-I multiplier consumes the least power. It is also found that the optimum digit-size for least power consumption in type-I and type-III multipliers is approximately √2W, where W represents the word length. The proposed digit-serial multipliers consume on an average 1.75 times lower power than the traditional digit-serial architectures for the non-pipelined case, and about 15 times lower power for the bit-level pipelined case.

Original languageEnglish (US)
Pages (from-to)2164-2167
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume3
StatePublished - Jan 1 1997

Fingerprint

Electric power utilization
Digital signal processing
Sampling
Feedback
Electric potential

Cite this

Low-power digit-serial multipliers. / Chang, Yun Nan; Satyanarayana, Janardhan H.; Parhi, Keshab K.

In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 3, 01.01.1997, p. 2164-2167.

Research output: Contribution to journalArticle

Chang, Yun Nan ; Satyanarayana, Janardhan H. ; Parhi, Keshab K. / Low-power digit-serial multipliers. In: Proceedings - IEEE International Symposium on Circuits and Systems. 1997 ; Vol. 3. pp. 2164-2167.
@article{131f79f15ed54b01b8627c2b18ee6ad8,
title = "Low-power digit-serial multipliers",
abstract = "Digit-serial implementation styles are best suited for implementation of digital signal processing systems which require moderate sampling rates. Digit-serial multipliers obtained using traditional unfolding techniques cannot be pipelined beyond a certain level because of the presence of feedback loops. In this paper, an alternative approach for the design of digit-serial multipliers is presented based on a novel cell replacement transformation. This transformation permits bit-level pipelining of the digit-serial multipliers thereby achieving sample speeds close to corresponding bit-parallel multipliers with significantly lower area. This increased sample speed can be traded with reduction in power supply voltage resulting in significant reduction in power consumption. The results show that for smaller digit-sizes (≤4), the type-II multiplier consumes the least power and for larger digit-sizes, the type-I multiplier consumes the least power. It is also found that the optimum digit-size for least power consumption in type-I and type-III multipliers is approximately √2W, where W represents the word length. The proposed digit-serial multipliers consume on an average 1.75 times lower power than the traditional digit-serial architectures for the non-pipelined case, and about 15 times lower power for the bit-level pipelined case.",
author = "Chang, {Yun Nan} and Satyanarayana, {Janardhan H.} and Parhi, {Keshab K}",
year = "1997",
month = "1",
day = "1",
language = "English (US)",
volume = "3",
pages = "2164--2167",
journal = "Proceedings - IEEE International Symposium on Circuits and Systems",
issn = "0271-4310",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - Low-power digit-serial multipliers

AU - Chang, Yun Nan

AU - Satyanarayana, Janardhan H.

AU - Parhi, Keshab K

PY - 1997/1/1

Y1 - 1997/1/1

N2 - Digit-serial implementation styles are best suited for implementation of digital signal processing systems which require moderate sampling rates. Digit-serial multipliers obtained using traditional unfolding techniques cannot be pipelined beyond a certain level because of the presence of feedback loops. In this paper, an alternative approach for the design of digit-serial multipliers is presented based on a novel cell replacement transformation. This transformation permits bit-level pipelining of the digit-serial multipliers thereby achieving sample speeds close to corresponding bit-parallel multipliers with significantly lower area. This increased sample speed can be traded with reduction in power supply voltage resulting in significant reduction in power consumption. The results show that for smaller digit-sizes (≤4), the type-II multiplier consumes the least power and for larger digit-sizes, the type-I multiplier consumes the least power. It is also found that the optimum digit-size for least power consumption in type-I and type-III multipliers is approximately √2W, where W represents the word length. The proposed digit-serial multipliers consume on an average 1.75 times lower power than the traditional digit-serial architectures for the non-pipelined case, and about 15 times lower power for the bit-level pipelined case.

AB - Digit-serial implementation styles are best suited for implementation of digital signal processing systems which require moderate sampling rates. Digit-serial multipliers obtained using traditional unfolding techniques cannot be pipelined beyond a certain level because of the presence of feedback loops. In this paper, an alternative approach for the design of digit-serial multipliers is presented based on a novel cell replacement transformation. This transformation permits bit-level pipelining of the digit-serial multipliers thereby achieving sample speeds close to corresponding bit-parallel multipliers with significantly lower area. This increased sample speed can be traded with reduction in power supply voltage resulting in significant reduction in power consumption. The results show that for smaller digit-sizes (≤4), the type-II multiplier consumes the least power and for larger digit-sizes, the type-I multiplier consumes the least power. It is also found that the optimum digit-size for least power consumption in type-I and type-III multipliers is approximately √2W, where W represents the word length. The proposed digit-serial multipliers consume on an average 1.75 times lower power than the traditional digit-serial architectures for the non-pipelined case, and about 15 times lower power for the bit-level pipelined case.

UR - http://www.scopus.com/inward/record.url?scp=0030655267&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0030655267&partnerID=8YFLogxK

M3 - Article

VL - 3

SP - 2164

EP - 2167

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

SN - 0271-4310

ER -