Clock networks account for a significant fraction of the power dissipation of a chip and are critical to performance. This paper presents theory and algorithms for building a low-power clock tree by distributing the clock signal at a lower voltage and translating it to a higher voltage at the utilization points. Two low-power schemes are used: reduced swing and multiple-supply voltages. We analyze the issue of tree construction and present conclusions relevant to various technology generations according to the NTRS. Our experimental results show that power savings of an average of 45% are possible for a 0.25 μm technology using multiple supply voltages, and about 32% using a single external supply voltage.
|Original language||English (US)|
|Number of pages||10|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|State||Published - Jun 2002|
Bibliographical noteFunding Information:
Manuscript received July 1999; revised November 14, 2000. This work was supported in part by the SRC under Contract 98-DJ-609, by the NSF under Award CCR-9800992, and by a scholarship from the Royal Thai Air Force. The authors are with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA. Publisher Item Identifier S 1063-8210(02)03192-X.
Copyright 2008 Elsevier B.V., All rights reserved.
- Clock networks
- Clock skew
- Dual supply voltages
- High-performance interconnect
- Low-power design
- Very large scale integration (VLSI)