LOW-POWER BIT-SERIAL VITERBI DECODER FOR NEXT GENERATION WIDE-BAND CDMA SYSTEMS

Hiroshi Suzuki, Yun Nan Chang, Keshab K. Parhi

Research output: Contribution to journalConference articlepeer-review

1 Scopus citations

Abstract

This paper presents a low-power bit-serial Viterbi decoder chip with the coding rate r = 1/3 and the constraint length K = 9 (256 states). This chip has been implemented using 0.5pm three-layer metal CMOS technology and is targeted for high speed convolutional decoding for next generation wireless applications such as wide-band CDMA mobile systems and wireless ATM LANs. The chip is expected to operate at 2OMbps under 3.3V and at 2Mbps under 1.8V. The Add-Compare-Select (ACS) units have been designed using bit-serial arithmetic, which has made it feasible to execute 256 ACS operations in parallel. For trace-back operations, we have developed a novel power-efficient trace-back scheme and an application-specijic memory, which was designed considering that 256 bits should be written simultaneously for write operations but only one bit needs to be accessed for read operations. We have estimated that the chip dissipates only lOmW at 2Mbps operation under 1.8V.

Original languageEnglish (US)
Pages (from-to)1913-1916
Number of pages4
JournalICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Volume4
DOIs
StatePublished - 1999
EventProceedings of the 1999 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP-99) - Phoenix, AZ, USA
Duration: Mar 15 1999Mar 19 1999

Bibliographical note

Publisher Copyright:
© 1999 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.

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