Abstract
This paper explores various low power higher order compressors such as 4-2 and 5-2 compressor units. These compressors are building blocks for binary multipliers. Various circuit architectures for 4-2 compressors are compared with respect to their delay and power consumption. The different circuits are simulated using HSPICE. A new circuit for 5-2 compressor is then presented which is 12% faster and consumes 37% less power.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 129-133 |
| Number of pages | 5 |
| Journal | Conference Record of the Asilomar Conference on Signals, Systems and Computers |
| Volume | 1 |
| DOIs | |
| State | Published - 2001 |