Low-latency successive-cancellation polar decoder architectures using 2-bit decoding

Keyphrases

• Low Latency 100%
• Decoder 100%
• Encoder-decoder Architecture 100%
• 2-bit 100%
• Polar Decoder 100%
• Successive Cancellation 100%
• Bit Decoding 100%
• Precomputation 66%
• Successive Cancellation Algorithm 50%
• Latency 33%
• Polar Codes 33%
• Successive Cancellation Decoder 33%
• Hardware Efficiency 33%
• High-throughput 16%
• Error Correction Codes 16%
• Hardware Complexity 16%
• Hardware Design 16%
• Long Latency 16%
• Reduced Latency 16%
• Look-ahead Algorithm 16%
• Performance Loss 16%
• 1-bit 16%
• Capacity-achieving 16%
• Successive-cancellation Decoding 16%
• Throughput Efficiency 16%
• Path Complexity 16%

Engineering

• Reformulation 100%
• Hardware Complexity 50%
• Performance Loss 50%
• Correction Code 50%
• Error Correction 50%
• Critical Path 50%

Computer Science

• Precomputation 100%
• Computer Hardware 75%
• High Throughput 25%
• Hardware Design 25%
• Critical Path 25%
• Good Candidate 25%
• Error Correction Code 25%
• Performance Loss 25%