Low-latency successive-cancellation polar decoder architectures using 2-bit decoding

Research output: Contribution to journalArticle

55 Citations (Scopus)

Abstract

Polar codes have emerged as important error correction codes due to their capacity-achieving property. Successive cancellation (SC) algorithm is viewed as a good candidate for hardware design of polar decoders due to its low complexity. However, for (n, k) polar codes, the long latency of SC algorithm of (2n-2) is a bottleneck for designing high-throughput polar decoder. In this paper, we present a novel reformulation for the last stage of SC decoding. The proposed reformulation leads to two benefits. First, critical path and hardware complexity in the last stage of SC algorithm is significantly reduced. Second, 2 bits can be decoded simultaneously instead of 1 bit. As a result, this new decoder, referred to as 2b-SC decoder, reduces latency from (2n-2) to (1.5n-2) without performance loss. Additionally, overlapped-scheduling, precomputation and look-ahead techniques are used to design two additional decoders referred to as 2b-SC-Overlapped-scheduling decoder and 2b-SC-Precomputation decoder, respectively. All three architectures offer significant advantages with respect to throughput and hardware efficiency. Compared to known prior least-latency SC decoder, the 2b-SC-Precomputation decoder has 25% less latency. Synthesis results show that the proposed (1024, 512) 2b-SC-Precomputation decoder can achieve at least 4 times increase in throughput and 40% increase in hardware efficiency.

Original languageEnglish (US)
Article number6632947
Pages (from-to)1241-1254
Number of pages14
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume61
Issue number4
DOIs
StatePublished - Jan 1 2014

Fingerprint

Decoding
Hardware
Throughput
Scheduling
Error correction

Keywords

  • 2-bit decoder
  • Look-ahead
  • overlapped scheduling
  • polar codes
  • precomputation
  • successive cancellation

Cite this

Low-latency successive-cancellation polar decoder architectures using 2-bit decoding. / Yuan, Bo; Parhi, Keshab K.

In: IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 61, No. 4, 6632947, 01.01.2014, p. 1241-1254.

Research output: Contribution to journalArticle

@article{a903981b1d0341ce8ce48181857e3e2f,
title = "Low-latency successive-cancellation polar decoder architectures using 2-bit decoding",
abstract = "Polar codes have emerged as important error correction codes due to their capacity-achieving property. Successive cancellation (SC) algorithm is viewed as a good candidate for hardware design of polar decoders due to its low complexity. However, for (n, k) polar codes, the long latency of SC algorithm of (2n-2) is a bottleneck for designing high-throughput polar decoder. In this paper, we present a novel reformulation for the last stage of SC decoding. The proposed reformulation leads to two benefits. First, critical path and hardware complexity in the last stage of SC algorithm is significantly reduced. Second, 2 bits can be decoded simultaneously instead of 1 bit. As a result, this new decoder, referred to as 2b-SC decoder, reduces latency from (2n-2) to (1.5n-2) without performance loss. Additionally, overlapped-scheduling, precomputation and look-ahead techniques are used to design two additional decoders referred to as 2b-SC-Overlapped-scheduling decoder and 2b-SC-Precomputation decoder, respectively. All three architectures offer significant advantages with respect to throughput and hardware efficiency. Compared to known prior least-latency SC decoder, the 2b-SC-Precomputation decoder has 25{\%} less latency. Synthesis results show that the proposed (1024, 512) 2b-SC-Precomputation decoder can achieve at least 4 times increase in throughput and 40{\%} increase in hardware efficiency.",
keywords = "2-bit decoder, Look-ahead, overlapped scheduling, polar codes, precomputation, successive cancellation",
author = "Bo Yuan and Parhi, {Keshab K}",
year = "2014",
month = "1",
day = "1",
doi = "10.1109/TCSI.2013.2283779",
language = "English (US)",
volume = "61",
pages = "1241--1254",
journal = "IEEE Transactions on Circuits and Systems I: Regular Papers",
issn = "1549-8328",
number = "4",

}

TY - JOUR

T1 - Low-latency successive-cancellation polar decoder architectures using 2-bit decoding

AU - Yuan, Bo

AU - Parhi, Keshab K

PY - 2014/1/1

Y1 - 2014/1/1

N2 - Polar codes have emerged as important error correction codes due to their capacity-achieving property. Successive cancellation (SC) algorithm is viewed as a good candidate for hardware design of polar decoders due to its low complexity. However, for (n, k) polar codes, the long latency of SC algorithm of (2n-2) is a bottleneck for designing high-throughput polar decoder. In this paper, we present a novel reformulation for the last stage of SC decoding. The proposed reformulation leads to two benefits. First, critical path and hardware complexity in the last stage of SC algorithm is significantly reduced. Second, 2 bits can be decoded simultaneously instead of 1 bit. As a result, this new decoder, referred to as 2b-SC decoder, reduces latency from (2n-2) to (1.5n-2) without performance loss. Additionally, overlapped-scheduling, precomputation and look-ahead techniques are used to design two additional decoders referred to as 2b-SC-Overlapped-scheduling decoder and 2b-SC-Precomputation decoder, respectively. All three architectures offer significant advantages with respect to throughput and hardware efficiency. Compared to known prior least-latency SC decoder, the 2b-SC-Precomputation decoder has 25% less latency. Synthesis results show that the proposed (1024, 512) 2b-SC-Precomputation decoder can achieve at least 4 times increase in throughput and 40% increase in hardware efficiency.

AB - Polar codes have emerged as important error correction codes due to their capacity-achieving property. Successive cancellation (SC) algorithm is viewed as a good candidate for hardware design of polar decoders due to its low complexity. However, for (n, k) polar codes, the long latency of SC algorithm of (2n-2) is a bottleneck for designing high-throughput polar decoder. In this paper, we present a novel reformulation for the last stage of SC decoding. The proposed reformulation leads to two benefits. First, critical path and hardware complexity in the last stage of SC algorithm is significantly reduced. Second, 2 bits can be decoded simultaneously instead of 1 bit. As a result, this new decoder, referred to as 2b-SC decoder, reduces latency from (2n-2) to (1.5n-2) without performance loss. Additionally, overlapped-scheduling, precomputation and look-ahead techniques are used to design two additional decoders referred to as 2b-SC-Overlapped-scheduling decoder and 2b-SC-Precomputation decoder, respectively. All three architectures offer significant advantages with respect to throughput and hardware efficiency. Compared to known prior least-latency SC decoder, the 2b-SC-Precomputation decoder has 25% less latency. Synthesis results show that the proposed (1024, 512) 2b-SC-Precomputation decoder can achieve at least 4 times increase in throughput and 40% increase in hardware efficiency.

KW - 2-bit decoder

KW - Look-ahead

KW - overlapped scheduling

KW - polar codes

KW - precomputation

KW - successive cancellation

UR - http://www.scopus.com/inward/record.url?scp=84897573544&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84897573544&partnerID=8YFLogxK

U2 - 10.1109/TCSI.2013.2283779

DO - 10.1109/TCSI.2013.2283779

M3 - Article

VL - 61

SP - 1241

EP - 1254

JO - IEEE Transactions on Circuits and Systems I: Regular Papers

JF - IEEE Transactions on Circuits and Systems I: Regular Papers

SN - 1549-8328

IS - 4

M1 - 6632947

ER -