Low error fixed-width modified Booth multiplier

K. J. Cho, K. C. Lee, J. G. Chung, K. K. Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

This paper presents an error compensation method for a modified Booth fixed-width multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, Booth encoder outputs (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups depending upon their effects on the quantization error. Then, different error compensation methods are applied to each group. By simulations, it is shown that quantization error can be reduced up to 50% by the proposed error compensation method compared with the existing method with slight increase in the overhead of bias generation circuit.

Original languageEnglish (US)
Title of host publicationIEEE Workshop on Signal Processing Systems, SIPS 2002
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages45-50
Number of pages6
ISBN (Electronic)0780375874
DOIs
StatePublished - Jan 1 2002
Event16th IEEE Workshop on Signal Processing Systems, SIPS 2002 - San Diego, United States
Duration: Oct 16 2002Oct 18 2002

Publication series

NameIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
Volume2002-January
ISSN (Print)1520-6130

Other

Other16th IEEE Workshop on Signal Processing Systems, SIPS 2002
CountryUnited States
CitySan Diego
Period10/16/0210/18/02

Keywords

  • Adders
  • Circuit simulation
  • Digital signal processing
  • Error compensation
  • Finite wordlength effects
  • Linear regression
  • Quantization
  • Signal generators
  • Statistical analysis
  • USA Councils

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