Abstract
This paper presents an error compensation method for a modified Booth fixed-width multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, Booth encoder outputs (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups depending upon their effects on the quantization error. Then, different error compensation methods are applied to each group. By simulations, it is shown that quantization error can be reduced up to 50% by the proposed error compensation method compared with the existing method with slight increase in the overhead of bias generation circuit.
| Original language | English (US) |
|---|---|
| Title of host publication | IEEE Workshop on Signal Processing Systems, SIPS 2002 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 45-50 |
| Number of pages | 6 |
| ISBN (Electronic) | 0780375874 |
| DOIs | |
| State | Published - 2002 |
| Event | 16th IEEE Workshop on Signal Processing Systems, SIPS 2002 - San Diego, United States Duration: Oct 16 2002 → Oct 18 2002 |
Publication series
| Name | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation |
|---|---|
| Volume | 2002-January |
| ISSN (Print) | 1520-6130 |
Other
| Other | 16th IEEE Workshop on Signal Processing Systems, SIPS 2002 |
|---|---|
| Country/Territory | United States |
| City | San Diego |
| Period | 10/16/02 → 10/18/02 |
Bibliographical note
Publisher Copyright:© 2002 IEEE.
Keywords
- Adders
- Circuit simulation
- Digital signal processing
- Error compensation
- Finite wordlength effects
- Linear regression
- Quantization
- Signal generators
- Statistical analysis
- USA Councils