This paper presents an error compensation method for fixed-width canonic signed digit (CSD) multipliers that receive a W-bit input and produce a W-bit product. To efficiently compensate for the quantization error, the truncated bits are divided into two groups (major group and minor group) depending upon their effects on the quantization error. The desired error compensation bias is first expressed in terms of the truncated bits in the major group. Then the effects of the other truncated bits in the minor group are taken care of by a probabilistic estimation. Also, an efficient sign extension reduction method applied to the fixed-width CSD multipliers is proposed. By simulations, it is shown that 25% reduction in the truncation error and 13% hardware complexity can be achieved by the proposed error compensation and sign extension reduction methods, respectively.
|Original language||English (US)|
|Number of pages||10|
|Journal||IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing|
|State||Published - Dec 2003|
Bibliographical noteFunding Information:
Manuscript received July 23, 2002; revised August 12, 2003. This work was supported by the National Science Foundation under Contract CCR-9988262. This paper was recommended by Associate Editor Y. Wang.
- Canonic signed digit (CSD)
- Error compensation bias
- Fixed-width multiplier