TY - JOUR

T1 - Low-energy programmable finite field data path architectures

AU - Song, Leilei

AU - Parhi, Keshab K

AU - Kuroda, Ichiro

AU - Nishitani, Takao

PY - 1998/1/1

Y1 - 1998/1/1

N2 - This paper considers implementation of finite field multiplication data paths in a domain-specific programmable digital signal processor (DS-PDSP), where special hardware units and corresponding instructions are assumed to be used to program finite field multiplication operation. These multiplication data paths are designed to accommodate programmability with respect to the primitive polynomial as well as the field order. Three types of multipliers are considered; these include semi-systolic array (in both least-significant-bit first and most-significant-bit first modes), fully-parallel, and the proposed approach where polynomial multiplication and polynomial modulo operations are implemented separately and two instructions, MAC and DEGRED are assigned to them, respectively. Two approaches are considered for achieving programmability with respect to the field order, either with special control circuitry, or with pre- and post-logical shifting operations. It is concluded that the one-level pipelined fully-parallel multiplier without control circuitry consumes the least energy at component level when only one multiplication is considered. However, at system level, when vector-vector multiplications, common in most DSP algorithms, are considered, the proposed approach is able to achieve 70% energy reduction at the expense of increasing the total instruction count by one.

AB - This paper considers implementation of finite field multiplication data paths in a domain-specific programmable digital signal processor (DS-PDSP), where special hardware units and corresponding instructions are assumed to be used to program finite field multiplication operation. These multiplication data paths are designed to accommodate programmability with respect to the primitive polynomial as well as the field order. Three types of multipliers are considered; these include semi-systolic array (in both least-significant-bit first and most-significant-bit first modes), fully-parallel, and the proposed approach where polynomial multiplication and polynomial modulo operations are implemented separately and two instructions, MAC and DEGRED are assigned to them, respectively. Two approaches are considered for achieving programmability with respect to the field order, either with special control circuitry, or with pre- and post-logical shifting operations. It is concluded that the one-level pipelined fully-parallel multiplier without control circuitry consumes the least energy at component level when only one multiplication is considered. However, at system level, when vector-vector multiplications, common in most DSP algorithms, are considered, the proposed approach is able to achieve 70% energy reduction at the expense of increasing the total instruction count by one.

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M3 - Article

AN - SCOPUS:0031623041

SN - 0271-4310

VL - 2

SP - 406

EP - 409

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

ER -