Digit-serial architectures are best suited for systems requiring moderate sample rate and where area and power consumption are critical. This paper presents a new approach for designing digit-serial/parallel finite field multipliers. This approach combines both array-type and parallel multiplication algorithms, where the digitlevel array-type algorithm minimizes the latency for one multiplication operation and the parallel architecture inside of each digit cell reduces both the cycle-time as well as the switching activities, hence power consumption. By appropriately constraining the feasible primitive polynomials, the mod p(x) operation involved in finite field multiplication can be performed in a more efficient way. As a result, the computation delay and energy consumption of one finite field multiplication using the proposed digit-serial/parallel architectures are significantly less than of those obtained by folding the parallel semi-systolic multipliers. Furthermore, their energy-delay products are reduced by a even larger percentage. Therefore, the proposed digit-serial/parallel architectures are attractive for both low-energy and high-performance applications.
|Original language||English (US)|
|Number of pages||18|
|Journal||Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology|
|State||Published - 1998|
Bibliographical noteFunding Information:
This research was supported by Army Research Office under grant number DA/DAAH-94-G-0405.
Copyright 2012 Elsevier B.V., All rights reserved.