Low-energy architectures for Support Vector Machine computation

Manohar Ayinala, Keshab K. Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations


This brief presents a novel architecture for Support Vector Machines (SVMs), a machine learning algorithm that performs classification tasks. SVMs achieve very good classification accuracy at the cost of high computational complexity. We propose a low-energy architecture based on approximate computing by exploiting the inherent error resilience in the SVM computation. We present two design optimizations, fixed-width multiply-add and non-uniform look-up table (LUT) for exponent function to minimize power consumption and hardware complexity while retaining the classification performance. A novel non-uniform quantization scheme is proposed for implementing the exponent function which reduces the size of the look-up table by 50%. The proposed non-uniform look-up table reduces the power consumption by 35% using 10-bit quantization. The proposed architecture is programmable and can evaluate three different kernels (linear, polynomial, radial basis function (RBF)). The proposed design consumes 31% less energy on average compared to a conventional design. We estimate that SVM computation using RBF kernel can be performed in 382.2nJ for 36 features and 5000 support vectors using 65nm technology.

Original languageEnglish (US)
Title of host publicationConference Record of the 47th Asilomar Conference on Signals, Systems and Computers
PublisherIEEE Computer Society
Number of pages5
ISBN (Print)9781479923908
StatePublished - Jan 1 2013
Event2013 47th Asilomar Conference on Signals, Systems and Computers - Pacific Grove, CA, United States
Duration: Nov 3 2013Nov 6 2013

Publication series

NameConference Record - Asilomar Conference on Signals, Systems and Computers
ISSN (Print)1058-6393


Other2013 47th Asilomar Conference on Signals, Systems and Computers
Country/TerritoryUnited States
CityPacific Grove, CA


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