Low-cost parallel FIR filter structures with 2-stage parallelism

Chao Cheng, Keshab K Parhi

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Abstract

Based on recently published low-complexity parallel finite-impulse response (FIR) filter structures, this paper proposes a new parallel FIR Filter structure with less hardware complexity. The subfilters in the previous parallel FIR structures are replaced by a second stage parallel FIR filter. The proposed 2-stage parallel FIR filter structures can efficiently reduce the number of required multiplications and additions at the expense of delay elements. For a 32-parallel 1152-tap FIR filter, the proposed structure can save 5184 multiplications (67%), 2612 additions (30%), compared to previous parallel FIR structures, at the expense of 10089 delay elements (-133%). The proposed structures will lead to significant hardware savings because the hardware cost of a delay element is only a small portion of that of a multiplier, not including the savings in the number of additions.

Original languageEnglish (US)
Pages (from-to)280-290
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume54
Issue number2
DOIs
StatePublished - Feb 1 2007

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Keywords

  • Fast convolution
  • Iterated short convolution (ISC)
  • Parallel finite-impulse response (FIR)
  • VLSI

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