Abstract
Based on recently published low-complexity parallel finite-impulse response (FIR) filter structures, this paper proposes a new parallel FIR Filter structure with less hardware complexity. The subfilters in the previous parallel FIR structures are replaced by a second stage parallel FIR filter. The proposed 2-stage parallel FIR filter structures can efficiently reduce the number of required multiplications and additions at the expense of delay elements. For a 32-parallel 1152-tap FIR filter, the proposed structure can save 5184 multiplications (67%), 2612 additions (30%), compared to previous parallel FIR structures, at the expense of 10089 delay elements (-133%). The proposed structures will lead to significant hardware savings because the hardware cost of a delay element is only a small portion of that of a multiplier, not including the savings in the number of additions.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 280-290 |
| Number of pages | 11 |
| Journal | IEEE Transactions on Circuits and Systems I: Regular Papers |
| Volume | 54 |
| Issue number | 2 |
| DOIs | |
| State | Published - Feb 2007 |
Bibliographical note
Funding Information:Manuscript received February 8, 2006; revised June 20, 2006. This work was supported in part by National Science Foundation Grand CCF-0429979. This paper was recommended by Associate Editor J. R. Chen. The authors are with Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis MN 55455 USA (e-mail: chao@ece.umn.edu; parhi@ece.umn.edu). Digital Object Identifier 10.1109/TCSI.2006.885976
Keywords
- Fast convolution
- Iterated short convolution (ISC)
- Parallel finite-impulse response (FIR)
- VLSI