TY - JOUR

T1 - Low-cost fast VLSI algorithm for discrete fourier transform

AU - Cheng, Chao

AU - Parhi, Keshab K.

PY - 2007/4

Y1 - 2007/4

N2 - A prime N-length discrete Fourier transform (DFT) can be reformulated into a (N-1)-length complex cyclic convolution and then implemented by systolic array or distributed arithmetic. In this paper, a recently proposed hardware efficient fast cyclic convolution algorithm is combined with the symmetry properties of DFT to get a new hardware efficient fast algorithm for small-length DFT, and then WFTA is used to control the increase of the hardware cost when the transform length N is large. Compared with previously proposed low-cost DFT and FFT algorithms with computation complexity of O(log N), the new algorithm can save 30% to 50% multipliers on average and improve the average processing speed by a factor of 2, when DFT length N varies from 20 to 2040. Compared with previous prime-length DFT design, the proposed design can save large amount of hardware cost with the same processing speed when the transform length is long. Furthermore, the proposed design has much more choices for different applicable DFT transform lengths and the processing speed can be flexible and balanced with the hardware cost.

AB - A prime N-length discrete Fourier transform (DFT) can be reformulated into a (N-1)-length complex cyclic convolution and then implemented by systolic array or distributed arithmetic. In this paper, a recently proposed hardware efficient fast cyclic convolution algorithm is combined with the symmetry properties of DFT to get a new hardware efficient fast algorithm for small-length DFT, and then WFTA is used to control the increase of the hardware cost when the transform length N is large. Compared with previously proposed low-cost DFT and FFT algorithms with computation complexity of O(log N), the new algorithm can save 30% to 50% multipliers on average and improve the average processing speed by a factor of 2, when DFT length N varies from 20 to 2040. Compared with previous prime-length DFT design, the proposed design can save large amount of hardware cost with the same processing speed when the transform length is long. Furthermore, the proposed design has much more choices for different applicable DFT transform lengths and the processing speed can be flexible and balanced with the hardware cost.

KW - Cyclic convolution

KW - Discrete Fourier transforms (DFTs)

KW - Systolic array

KW - VLSI

UR - http://www.scopus.com/inward/record.url?scp=34247238158&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34247238158&partnerID=8YFLogxK

U2 - 10.1109/TCSI.2006.888772

DO - 10.1109/TCSI.2006.888772

M3 - Article

AN - SCOPUS:34247238158

SN - 1549-8328

VL - 54

SP - 791

EP - 806

JO - IEEE Transactions on Circuits and Systems I: Regular Papers

JF - IEEE Transactions on Circuits and Systems I: Regular Papers

IS - 4

ER -