Low-cost fast VLSI algorithm for discrete fourier transform

Chao Cheng, Keshab K. Parhi

Research output: Contribution to journalArticle

24 Scopus citations

Abstract

A prime N-length discrete Fourier transform (DFT) can be reformulated into a (N-1)-length complex cyclic convolution and then implemented by systolic array or distributed arithmetic. In this paper, a recently proposed hardware efficient fast cyclic convolution algorithm is combined with the symmetry properties of DFT to get a new hardware efficient fast algorithm for small-length DFT, and then WFTA is used to control the increase of the hardware cost when the transform length N is large. Compared with previously proposed low-cost DFT and FFT algorithms with computation complexity of O(log N), the new algorithm can save 30% to 50% multipliers on average and improve the average processing speed by a factor of 2, when DFT length N varies from 20 to 2040. Compared with previous prime-length DFT design, the proposed design can save large amount of hardware cost with the same processing speed when the transform length is long. Furthermore, the proposed design has much more choices for different applicable DFT transform lengths and the processing speed can be flexible and balanced with the hardware cost.

Original languageEnglish (US)
Pages (from-to)791-806
Number of pages16
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume54
Issue number4
DOIs
StatePublished - Apr 1 2007

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Keywords

  • Cyclic convolution
  • Discrete Fourier transforms (DFTs)
  • Systolic array
  • VLSI

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