Low cost ECC schemes for improving the reliability of DRAM+PRAMMAIN memory systems

Manqing Mao; Chengen Yang; Zihan Xu; Yu Cao; Chaitali Chakrabarti

doi:10.1109/SiPS.2014.6986076

Low cost ECC schemes for improving the reliability of DRAM+PRAMMAIN memory systems

Manqing Mao, Chengen Yang, Zihan Xu, Yu Cao, Chaitali Chakrabarti

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

Hybrid memory, where the DRAM acts as a buffer to the PRAM, is a promising configuration for main memory systems. It has the advantages of fast access time, high storage density and very low standby power. However, it also has reliability issues that need to be addressed. This paper focuses on low cost Error Control Coding (ECC)-based schemes for improving the reliability of hybrid memory. We propose three candidate systems that all guarantee block failure rate of 10^-8 but differ in whether the DRAM and/or PRAM data get coded and the strength of the corresponding ECC code. The candidate systems are evaluated with respect to lifetime, Instruction Per Cycle (IPC) and energy. We show that (1) at lower Data Storage Time (DST), the proposed system which has different ECC schemes for DRAM and PRAM has the longest lifetime and one of the highest IPC; (2) at higher DST, stronger ECC codes are necessary for all the systems and longer lifetime can be achieved at the cost of decrease in IPC.

Original language	English (US)
Title of host publication	IEEE Workshop on Signal Processing Systems, SiPS
Subtitle of host publication	Design and Implementation
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479965885
DOIs	https://doi.org/10.1109/SiPS.2014.6986076
State	Published - Dec 15 2014
Externally published	Yes
Event	2014 IEEE Workshop on Signal Processing Systems, SiPS 2014 - Belfast, United Kingdom Duration: Oct 20 2014 → Oct 22 2014

Publication series

Name	IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
ISSN (Print)	1520-6130

Conference

Conference	2014 IEEE Workshop on Signal Processing Systems, SiPS 2014
Country/Territory	United Kingdom
City	Belfast
Period	10/20/14 → 10/22/14

Bibliographical note

Publisher Copyright:
© 2014 IEEE.

Keywords

DRAM+PRAM
Hybrid main memory
error correction codes
reliability

Publisher link

10.1109/SiPS.2014.6986076

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Mao, M., Yang, C., Xu, Z., Cao, Y., & Chakrabarti, C. (2014). Low cost ECC schemes for improving the reliability of DRAM+PRAMMAIN memory systems. In IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation Article 6986076 (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SiPS.2014.6986076

Low cost ECC schemes for improving the reliability of DRAM+PRAMMAIN memory systems. / Mao, Manqing; Yang, Chengen; Xu, Zihan et al.
IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation. Institute of Electrical and Electronics Engineers Inc., 2014. 6986076 (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Mao, M, Yang, C, Xu, Z, Cao, Y & Chakrabarti, C 2014, Low cost ECC schemes for improving the reliability of DRAM+PRAMMAIN memory systems. in IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation., 6986076, IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, Institute of Electrical and Electronics Engineers Inc., 2014 IEEE Workshop on Signal Processing Systems, SiPS 2014, Belfast, United Kingdom, 10/20/14. https://doi.org/10.1109/SiPS.2014.6986076

Mao M, Yang C, Xu Z, Cao Y, Chakrabarti C. Low cost ECC schemes for improving the reliability of DRAM+PRAMMAIN memory systems. In IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation. Institute of Electrical and Electronics Engineers Inc. 2014. 6986076. (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation). doi: 10.1109/SiPS.2014.6986076

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N2 - Hybrid memory, where the DRAM acts as a buffer to the PRAM, is a promising configuration for main memory systems. It has the advantages of fast access time, high storage density and very low standby power. However, it also has reliability issues that need to be addressed. This paper focuses on low cost Error Control Coding (ECC)-based schemes for improving the reliability of hybrid memory. We propose three candidate systems that all guarantee block failure rate of 10-8 but differ in whether the DRAM and/or PRAM data get coded and the strength of the corresponding ECC code. The candidate systems are evaluated with respect to lifetime, Instruction Per Cycle (IPC) and energy. We show that (1) at lower Data Storage Time (DST), the proposed system which has different ECC schemes for DRAM and PRAM has the longest lifetime and one of the highest IPC; (2) at higher DST, stronger ECC codes are necessary for all the systems and longer lifetime can be achieved at the cost of decrease in IPC.

AB - Hybrid memory, where the DRAM acts as a buffer to the PRAM, is a promising configuration for main memory systems. It has the advantages of fast access time, high storage density and very low standby power. However, it also has reliability issues that need to be addressed. This paper focuses on low cost Error Control Coding (ECC)-based schemes for improving the reliability of hybrid memory. We propose three candidate systems that all guarantee block failure rate of 10-8 but differ in whether the DRAM and/or PRAM data get coded and the strength of the corresponding ECC code. The candidate systems are evaluated with respect to lifetime, Instruction Per Cycle (IPC) and energy. We show that (1) at lower Data Storage Time (DST), the proposed system which has different ECC schemes for DRAM and PRAM has the longest lifetime and one of the highest IPC; (2) at higher DST, stronger ECC codes are necessary for all the systems and longer lifetime can be achieved at the cost of decrease in IPC.

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Low cost ECC schemes for improving the reliability of DRAM+PRAMMAIN memory systems

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