The computational complexity of current iterative MIMO detector and channel estimator is high and the hardware design of MMSE soft detector with interference cancellation has not been discussed. This paper proposes a few techniques and their corresponding VLSI architectures to reduce the power consumption and computation time. First technique that is based on monitoring symbol mean and variance can reduce the complexity of iterative channel estimator and soft detector at the same time. The other two reuse previously computed information by loop or cache to simplify computation. Simulation results show these techniques can significantly reduce the computational complexity. The architecture of the soft detector and a low complexity low memory access channel estimator are also proposed. They are designed to reduce power consumption and computation time.