Low complexity design of high speed parallel decision feedback equalizers

Daesun Oh, Keshab K Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Scopus citations

Abstract

This paper proposes a novel parallel approach for pipelining of nested multiplexer loops to design high speed decision feedback equalizers (DFEs) based on look-ahead techniques. It is well known that the DFE is an efficient scheme to suppress intersymbol interference (ISI) in various communication and magnetic recording systems. However, the feedback loop within a DFE limits an upper bound of the achievable high speed in hardware implementation. A straightforward parallel implementation requires more hardware complexity. The novel proposed technique offers significant reduction of hardware complexity of 56% and 80% over the conventional parallel six-tap DFE architectures for 10 Gbps and 20 Gbps throughput, respectively.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006
Pages118-122
Number of pages5
DOIs
StatePublished - Dec 1 2006
EventIEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006 - Steamboat Springs, CO, United States
Duration: Sep 11 2006Sep 13 2006

Other

OtherIEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006
CountryUnited States
CitySteamboat Springs, CO
Period9/11/069/13/06

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    Oh, D., & Parhi, K. K. (2006). Low complexity design of high speed parallel decision feedback equalizers. In Proceedings - IEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006 (pp. 118-122). [4019502] https://doi.org/10.1109/ASAP.2006.43