### Abstract

This paper presents a new heuristic, concurrent, iterative loop-based scheduling and allocation algorithm for high-level synthesis of digital signal processing (DSP) architectures using heterogeneous functional units. In a heterogeneous architecture, functional units could be either bit-serial or digit-serial or bit-parallel. We assume a library of heterogeneous implementation style based functional units is available. Experiments show that this new heuristic synthesis approach generates optimal and near-optimal area solutions. Although optimum synthesis of such architectures were proposed recently using an integer linear programming (ILP) model, our method can produce similar solutions in one to two orders of magnitude less time, at the expense of sacrificing the cost optimality. We compare the solutions generated by the proposed algorithm with the optimal solutions generated by the ILP approach and other recent techniques. We have incorporated this new algorithm into the Minnesota ARchitecture Synthesis (MARS-II) system.

Original language | English (US) |
---|---|

Pages (from-to) | 2-7 |

Number of pages | 6 |

Journal | Proceedings of the IEEE Great Lakes Symposium on VLSI |

State | Published - Jan 1 1996 |

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### Cite this

*Proceedings of the IEEE Great Lakes Symposium on VLSI*, 2-7.

**Loop-list scheduling for heterogeneous functional units.** / Chang, Y. N.; Wang, Ch Y.; Parhi, Keshab K.

Research output: Contribution to journal › Article

*Proceedings of the IEEE Great Lakes Symposium on VLSI*, pp. 2-7.

}

TY - JOUR

T1 - Loop-list scheduling for heterogeneous functional units

AU - Chang, Y. N.

AU - Wang, Ch Y.

AU - Parhi, Keshab K

PY - 1996/1/1

Y1 - 1996/1/1

N2 - This paper presents a new heuristic, concurrent, iterative loop-based scheduling and allocation algorithm for high-level synthesis of digital signal processing (DSP) architectures using heterogeneous functional units. In a heterogeneous architecture, functional units could be either bit-serial or digit-serial or bit-parallel. We assume a library of heterogeneous implementation style based functional units is available. Experiments show that this new heuristic synthesis approach generates optimal and near-optimal area solutions. Although optimum synthesis of such architectures were proposed recently using an integer linear programming (ILP) model, our method can produce similar solutions in one to two orders of magnitude less time, at the expense of sacrificing the cost optimality. We compare the solutions generated by the proposed algorithm with the optimal solutions generated by the ILP approach and other recent techniques. We have incorporated this new algorithm into the Minnesota ARchitecture Synthesis (MARS-II) system.

AB - This paper presents a new heuristic, concurrent, iterative loop-based scheduling and allocation algorithm for high-level synthesis of digital signal processing (DSP) architectures using heterogeneous functional units. In a heterogeneous architecture, functional units could be either bit-serial or digit-serial or bit-parallel. We assume a library of heterogeneous implementation style based functional units is available. Experiments show that this new heuristic synthesis approach generates optimal and near-optimal area solutions. Although optimum synthesis of such architectures were proposed recently using an integer linear programming (ILP) model, our method can produce similar solutions in one to two orders of magnitude less time, at the expense of sacrificing the cost optimality. We compare the solutions generated by the proposed algorithm with the optimal solutions generated by the ILP approach and other recent techniques. We have incorporated this new algorithm into the Minnesota ARchitecture Synthesis (MARS-II) system.

UR - http://www.scopus.com/inward/record.url?scp=0029694860&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0029694860&partnerID=8YFLogxK

M3 - Article

SP - 2

EP - 7

JO - Proceedings of the IEEE Great Lakes Symposium on VLSI

JF - Proceedings of the IEEE Great Lakes Symposium on VLSI

SN - 1066-1395

ER -