Loop list scheduler for DSP algorithms under resource constraints

Ching Yi Wang; Keshab K Parhi

Loop list scheduler for DSP algorithms under resource constraints

Ching Yi Wang, Keshab K Parhi

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

We present a new algorithm for resource-constrained scheduling for DSP applications. We define new graph dependent constraints which directly results in the smallest iteration period for any data-flow graph. Previous synthesis systems have focused on simple DSP algorithms which contain no recursive loops or have single delays in the recursive loops. MARS is not restricted to such algorithms. This approach exploits inter-iteration and intra-iteration precedence constraints and incorporates implicit retiming and pipelining in generating optimal and near optimal schedules.

Original language	English (US)
Title of host publication	Proceedings - IEEE International Symposium on Circuits and Systems
Publisher	Publ by IEEE
Pages	1662-1665
Number of pages	4
Volume	3
ISBN (Print)	0780312813
State	Published - Jan 1 1993
Event	Proceedings of the 1993 IEEE International Symposium on Circuits and Systems - Chicago, IL, USA Duration: May 3 1993 → May 6 1993

Other

Other	Proceedings of the 1993 IEEE International Symposium on Circuits and Systems
City	Chicago, IL, USA
Period	5/3/93 → 5/6/93

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title = "Loop list scheduler for DSP algorithms under resource constraints",

abstract = "We present a new algorithm for resource-constrained scheduling for DSP applications. We define new graph dependent constraints which directly results in the smallest iteration period for any data-flow graph. Previous synthesis systems have focused on simple DSP algorithms which contain no recursive loops or have single delays in the recursive loops. MARS is not restricted to such algorithms. This approach exploits inter-iteration and intra-iteration precedence constraints and incorporates implicit retiming and pipelining in generating optimal and near optimal schedules.",

author = "Wang, {Ching Yi} and Parhi, {Keshab K}",

year = "1993",

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language = "English (US)",

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note = "Proceedings of the 1993 IEEE International Symposium on Circuits and Systems ; Conference date: 03-05-1993 Through 06-05-1993",

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T1 - Loop list scheduler for DSP algorithms under resource constraints

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AU - Parhi, Keshab K

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N2 - We present a new algorithm for resource-constrained scheduling for DSP applications. We define new graph dependent constraints which directly results in the smallest iteration period for any data-flow graph. Previous synthesis systems have focused on simple DSP algorithms which contain no recursive loops or have single delays in the recursive loops. MARS is not restricted to such algorithms. This approach exploits inter-iteration and intra-iteration precedence constraints and incorporates implicit retiming and pipelining in generating optimal and near optimal schedules.

AB - We present a new algorithm for resource-constrained scheduling for DSP applications. We define new graph dependent constraints which directly results in the smallest iteration period for any data-flow graph. Previous synthesis systems have focused on simple DSP algorithms which contain no recursive loops or have single delays in the recursive loops. MARS is not restricted to such algorithms. This approach exploits inter-iteration and intra-iteration precedence constraints and incorporates implicit retiming and pipelining in generating optimal and near optimal schedules.

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M3 - Conference contribution

AN - SCOPUS:0027266193

SN - 0780312813

VL - 3

SP - 1662

EP - 1665

BT - Proceedings - IEEE International Symposium on Circuits and Systems

PB - Publ by IEEE

T2 - Proceedings of the 1993 IEEE International Symposium on Circuits and Systems

Y2 - 3 May 1993 through 6 May 1993

ER -

Loop list scheduler for DSP algorithms under resource constraints

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