Abstract
A highly efficient loop-based interconnect modeling methodology is proposed for multigigahertz clock network design and optimization. Closed-form loop resistance and inductance models are proposed for fully shielded global clock interconnect structures, which capture high-frequency effects including inductance and proximity effects. The models are validated through comparisons with electromagnetic simulations and measured data taken from a Power4 chip. This modeling methodology greatly improves the clock interconnect simulation efficiency and enables fast physical design exploration. Examples of interconnect performance optimization are demonstrated and design guidelines are proposed.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 457-463 |
| Number of pages | 7 |
| Journal | IEEE Journal of Solid-State Circuits |
| Volume | 38 |
| Issue number | 3 |
| DOIs | |
| State | Published - Mar 2003 |
| Externally published | Yes |
Bibliographical note
Funding Information:Manuscript received July 25, 2002; revised October 25, 2002. This work was supported in part by the MARCO/DARPA Gigascale Silicon Research Center. X. Huang is with Rambus Inc., Los Altos, CA 94022 USA (e-mail: [email protected]). P. Restle and T. Bucelot are with the IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA. Y. Cao, T.-J. King, and C. Hu are with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 USA. Digital Object Identifier 10.1109/JSSC.2002.808313
Keywords
- Clock distribution
- Inductance
- Proximity effects
- Timing analysis