Loop-based interconnect modeling and optimization approach for multi-GHz clock network design

Xuejue Huang; Phillip Restle; Thomas Bucelot; Yu Cao; Tsu Jae King

doi:10.1109/CICC.2002.1012758

Loop-based interconnect modeling and optimization approach for multi-GHz clock network design

Xuejue Huang
, Phillip Restle
, Thomas Bucelot
, Yu Cao
, Tsu Jae King

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

An efficient loop-based interconnect modeling methodology is proposed for multi-GHz clock network design. High frequency effects, including inductance and proximity effects are captured. The results are validated through comparisons with electromagnetic simulations and measured data taken from a Power4 chip.

Original language	English (US)
Pages (from-to)	19-22
Number of pages	4
Journal	Proceedings of the Custom Integrated Circuits Conference
DOIs	https://doi.org/10.1109/CICC.2002.1012758
State	Published - 2002
Externally published	Yes

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10.1109/CICC.2002.1012758

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@article{9eaed84c9eb74a7aaff6b5dccae1ba93,

title = "Loop-based interconnect modeling and optimization approach for multi-GHz clock network design",

abstract = "An efficient loop-based interconnect modeling methodology is proposed for multi-GHz clock network design. High frequency effects, including inductance and proximity effects are captured. The results are validated through comparisons with electromagnetic simulations and measured data taken from a Power4 chip.",

author = "Xuejue Huang and Phillip Restle and Thomas Bucelot and Yu Cao and King, \{Tsu Jae\}",

year = "2002",

doi = "10.1109/CICC.2002.1012758",

language = "English (US)",

pages = "19--22",

journal = "Proceedings of the Custom Integrated Circuits Conference",

issn = "0886-5930",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - Loop-based interconnect modeling and optimization approach for multi-GHz clock network design

AU - Huang, Xuejue

AU - Restle, Phillip

AU - Bucelot, Thomas

AU - Cao, Yu

AU - King, Tsu Jae

PY - 2002

Y1 - 2002

N2 - An efficient loop-based interconnect modeling methodology is proposed for multi-GHz clock network design. High frequency effects, including inductance and proximity effects are captured. The results are validated through comparisons with electromagnetic simulations and measured data taken from a Power4 chip.

AB - An efficient loop-based interconnect modeling methodology is proposed for multi-GHz clock network design. High frequency effects, including inductance and proximity effects are captured. The results are validated through comparisons with electromagnetic simulations and measured data taken from a Power4 chip.

UR - https://www.scopus.com/pages/publications/0036045268

UR - https://www.scopus.com/pages/publications/0036045268#tab=citedBy

U2 - 10.1109/CICC.2002.1012758

DO - 10.1109/CICC.2002.1012758

M3 - Article

AN - SCOPUS:0036045268

SN - 0886-5930

SP - 19

EP - 22

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

ER -

Loop-based interconnect modeling and optimization approach for multi-GHz clock network design

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