Logical effort based technology mapping

Shrirang K. Karandikar, Sachin S Sapatnekar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Abstract

We propose a new approach to library-based technology mapping, based on the method of logical effort. Our algorithm is close to optimal for fanout-free circuits, and is extended to solve the load-distribution problem for circuits with fanout. On average, benchmark circuits mapped using our approach are 25.39% faster than the solutions obtained from SIS.

Original languageEnglish (US)
Title of host publicationICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
Pages419-422
Number of pages4
DOIs
StatePublished - Dec 1 2004
EventICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers - San Jose, CA, United States
Duration: Nov 7 2004Nov 11 2004

Publication series

NameIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
ISSN (Print)1092-3152

Other

OtherICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
CountryUnited States
CitySan Jose, CA
Period11/7/0411/11/04

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  • Cite this

    Karandikar, S. K., & Sapatnekar, S. S. (2004). Logical effort based technology mapping. In ICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers (pp. 419-422). [5D.2] (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD). https://doi.org/10.1109/ICCAD.2004.1382611