Abstract
Due to their capacity-achieving property, polar codes have become one of the most attractive channel codes. To date, the successive-cancellation list (SCL) decoding algorithm is the primary approach that can guarantee outstanding error-correcting performance of polar codes. However, the hardware designs of the original SCL decoder have a large silicon area and a long decoding latency. Although some recent efforts can reduce either the area or latency of SCL decoders, these two metrics still cannot be optimized at the same time. This brief, for the first time, proposes a general log-likelihood-ratio (LLR) based SCL decoding algorithm with multibit decision. This new algorithm, referred to as LLR-2K b-SCL, can determine 2K bits simultaneously for arbitrary K with the use of LLR messages. In addition, a reduced-data-width scheme is presented to reduce the critical path of the sorting block. Then, based on the proposed algorithm, a VLSI architecture of the new SCL decoder is developed. Synthesis results show that, for an example (1024, 512) polar code with list size 4, the proposed LLR-2K b-SCL decoders achieve a significant reduction in both area and latency as compared to prior works. As a result, the hardware efficiencies of the proposed designs with K= 2 and 3 are 2.33 times and 3.32 times of that of the state-of-the-art works, respectively.
| Original language | English (US) |
|---|---|
| Article number | 7440823 |
| Pages (from-to) | 21-25 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
| Volume | 64 |
| Issue number | 1 |
| DOIs | |
| State | Published - Jan 2017 |
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Keywords
- Log-likelihood-ratio (LLR)
- VLSI
- multibit decision
- polar codes
- successive-cancellation (SC)
Cite this
LLR-Based Successive-Cancellation List Decoder for Polar Codes with Multibit Decision. / Yuan, Bo; Parhi, Keshab K.
In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 64, No. 1, 7440823, 01.2017, p. 21-25.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - LLR-Based Successive-Cancellation List Decoder for Polar Codes with Multibit Decision
AU - Yuan, Bo
AU - Parhi, Keshab K.
PY - 2017/1
Y1 - 2017/1
N2 - Due to their capacity-achieving property, polar codes have become one of the most attractive channel codes. To date, the successive-cancellation list (SCL) decoding algorithm is the primary approach that can guarantee outstanding error-correcting performance of polar codes. However, the hardware designs of the original SCL decoder have a large silicon area and a long decoding latency. Although some recent efforts can reduce either the area or latency of SCL decoders, these two metrics still cannot be optimized at the same time. This brief, for the first time, proposes a general log-likelihood-ratio (LLR) based SCL decoding algorithm with multibit decision. This new algorithm, referred to as LLR-2K b-SCL, can determine 2K bits simultaneously for arbitrary K with the use of LLR messages. In addition, a reduced-data-width scheme is presented to reduce the critical path of the sorting block. Then, based on the proposed algorithm, a VLSI architecture of the new SCL decoder is developed. Synthesis results show that, for an example (1024, 512) polar code with list size 4, the proposed LLR-2K b-SCL decoders achieve a significant reduction in both area and latency as compared to prior works. As a result, the hardware efficiencies of the proposed designs with K= 2 and 3 are 2.33 times and 3.32 times of that of the state-of-the-art works, respectively.
AB - Due to their capacity-achieving property, polar codes have become one of the most attractive channel codes. To date, the successive-cancellation list (SCL) decoding algorithm is the primary approach that can guarantee outstanding error-correcting performance of polar codes. However, the hardware designs of the original SCL decoder have a large silicon area and a long decoding latency. Although some recent efforts can reduce either the area or latency of SCL decoders, these two metrics still cannot be optimized at the same time. This brief, for the first time, proposes a general log-likelihood-ratio (LLR) based SCL decoding algorithm with multibit decision. This new algorithm, referred to as LLR-2K b-SCL, can determine 2K bits simultaneously for arbitrary K with the use of LLR messages. In addition, a reduced-data-width scheme is presented to reduce the critical path of the sorting block. Then, based on the proposed algorithm, a VLSI architecture of the new SCL decoder is developed. Synthesis results show that, for an example (1024, 512) polar code with list size 4, the proposed LLR-2K b-SCL decoders achieve a significant reduction in both area and latency as compared to prior works. As a result, the hardware efficiencies of the proposed designs with K= 2 and 3 are 2.33 times and 3.32 times of that of the state-of-the-art works, respectively.
KW - Log-likelihood-ratio (LLR)
KW - VLSI
KW - multibit decision
KW - polar codes
KW - successive-cancellation (SC)
UR - http://www.scopus.com/inward/record.url?scp=85008449821&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85008449821&partnerID=8YFLogxK
U2 - 10.1109/TCSII.2016.2546904
DO - 10.1109/TCSII.2016.2546904
M3 - Article
AN - SCOPUS:85008449821
VL - 64
SP - 21
EP - 25
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
SN - 1549-8328
IS - 1
M1 - 7440823
ER -