Linear placement for static/dynamic reconfiguration in JBits

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Placement of functional units on an FPGA fabric is a challenging problem for runtime reconfigurable computing systems. We introduce the concept of physical contexts to greatly reduce the complexity of the placement and routing problems. We have implemented static and dynamic linear placement methods for expression trees placed in physical contexts. Our placement algorithms are implemented in the JBits environment, creating a layer of a hardware operating system for future reconfigurable computing systems.

Original languageEnglish (US)
Title of host publicationProceedings - 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2003
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages300-301
Number of pages2
ISBN (Electronic)0769519792
DOIs
StatePublished - Jan 1 2003
Event11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2003 - Napa, United States
Duration: Apr 9 2003Apr 11 2003

Publication series

NameIEEE Symposium on FPGAs for Custom Computing Machines, Proceedings
Volume2003-January
ISSN (Print)1082-3409

Other

Other11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2003
CountryUnited States
CityNapa
Period4/9/034/11/03

Keywords

  • Application software
  • Delay
  • Engines
  • Fabrics
  • Field programmable gate arrays
  • Hardware
  • Operating systems
  • Random access memory
  • Routing
  • Runtime

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  • Cite this

    Marreddy, V. K., Noorbaloochi, S., & Bazargan, K. (2003). Linear placement for static/dynamic reconfiguration in JBits. In Proceedings - 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2003 (pp. 300-301). [1227280] (IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings; Vol. 2003-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/FPGA.2003.1227280