Linear Characteristic Analysis of High-Resolution Counter-Based Frequency Detector in Type-I Digital PLL

Taehyoun Oh; Joonho Gil; Ramesh Harjani

doi:10.1109/TCSII.2021.3090056

Linear Characteristic Analysis of High-Resolution Counter-Based Frequency Detector in Type-I Digital PLL

Taehyoun Oh, Joonho Gil, Ramesh Harjani

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

This brief analyzes a linear characteristic of the high-resolution counter-based frequency detector (CBFD) using sinusoidal jitter. The theoretical gain of the Vernier-type CBFD can be derived by observing the output responses for the tone input in the time domain. A type-I digital phase locked loop (DPLL) using the CBFD is free from the issues related to the input static phase offset and the loop is unconditionally stable. Based on the loop dynamics of a DPLL with a CBFD (CB-DPLL), a jitter optimization in presence of phase noise of in-band and oscillator 1/f2 has been conducted. This analysis provides us with insights to design the CB-DPLL with the minimum output jitter.

Original language	English (US)
Pages (from-to)	264-268
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	69
Issue number	2
DOIs	https://doi.org/10.1109/TCSII.2021.3090056
State	Published - Feb 1 2022

Bibliographical note

Funding Information:
This work was supported in part by the National Research Foundation of Korea (NRF) grant funded by the Korea Government (MSIT) under Grant NRF-2020R1F1A1057497, and in part by the Research Grant of Kwangwoon University in 2020.

Publisher Copyright:
© 2021 IEEE.

Keywords

Additives
Detectors
Frequency control
Jitter
Phase locked loops
Steady-state
Timing

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title = "Linear Characteristic Analysis of High-Resolution Counter-Based Frequency Detector in Type-I Digital PLL",

abstract = "This brief analyzes a linear characteristic of the high-resolution counter-based frequency detector (CBFD) using sinusoidal jitter. The theoretical gain of the Vernier-type CBFD can be derived by observing the output responses for the tone input in the time domain. A type-I digital phase locked loop (DPLL) using the CBFD is free from the issues related to the input static phase offset and the loop is unconditionally stable. Based on the loop dynamics of a DPLL with a CBFD (CB-DPLL), a jitter optimization in presence of phase noise of in-band and oscillator 1/f2 has been conducted. This analysis provides us with insights to design the CB-DPLL with the minimum output jitter.",

keywords = "Additives, Detectors, Frequency control, Jitter, Phase locked loops, Steady-state, Timing",

author = "Taehyoun Oh and Joonho Gil and Ramesh Harjani",

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AU - Oh, Taehyoun

AU - Gil, Joonho

AU - Harjani, Ramesh

N1 - Funding Information: This work was supported in part by the National Research Foundation of Korea (NRF) grant funded by the Korea Government (MSIT) under Grant NRF-2020R1F1A1057497, and in part by the Research Grant of Kwangwoon University in 2020. Publisher Copyright: © 2021 IEEE.

PY - 2022/2/1

Y1 - 2022/2/1

N2 - This brief analyzes a linear characteristic of the high-resolution counter-based frequency detector (CBFD) using sinusoidal jitter. The theoretical gain of the Vernier-type CBFD can be derived by observing the output responses for the tone input in the time domain. A type-I digital phase locked loop (DPLL) using the CBFD is free from the issues related to the input static phase offset and the loop is unconditionally stable. Based on the loop dynamics of a DPLL with a CBFD (CB-DPLL), a jitter optimization in presence of phase noise of in-band and oscillator 1/f2 has been conducted. This analysis provides us with insights to design the CB-DPLL with the minimum output jitter.

AB - This brief analyzes a linear characteristic of the high-resolution counter-based frequency detector (CBFD) using sinusoidal jitter. The theoretical gain of the Vernier-type CBFD can be derived by observing the output responses for the tone input in the time domain. A type-I digital phase locked loop (DPLL) using the CBFD is free from the issues related to the input static phase offset and the loop is unconditionally stable. Based on the loop dynamics of a DPLL with a CBFD (CB-DPLL), a jitter optimization in presence of phase noise of in-band and oscillator 1/f2 has been conducted. This analysis provides us with insights to design the CB-DPLL with the minimum output jitter.

KW - Additives

KW - Detectors

KW - Frequency control

KW - Jitter

KW - Phase locked loops

KW - Steady-state

KW - Timing

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Linear Characteristic Analysis of High-Resolution Counter-Based Frequency Detector in Type-I Digital PLL

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