This brief analyzes a linear characteristic of the high-resolution counter-based frequency detector (CBFD) using sinusoidal jitter. The theoretical gain of the Vernier-type CBFD can be derived by observing the output responses for the tone input in the time domain. A type-I digital phase locked loop (DPLL) using the CBFD is free from the issues related to the input static phase offset and the loop is unconditionally stable. Based on the loop dynamics of a DPLL with a CBFD (CB-DPLL), a jitter optimization in presence of phase noise of in-band and oscillator 1/f2 has been conducted. This analysis provides us with insights to design the CB-DPLL with the minimum output jitter.
|Original language||English (US)|
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|State||Published - Feb 1 2022|
Bibliographical noteFunding Information:
This work was supported in part by the National Research Foundation of Korea (NRF) grant funded by the Korea Government (MSIT) under Grant NRF-2020R1F1A1057497, and in part by the Research Grant of Kwangwoon University in 2020.
© 2021 IEEE.
- Frequency control
- Phase locked loops