Hierarchical systems address many hardware and software problems encountered by designers of large communication and computing systems; hence, interest in this field continues to grow. A diversity of hierarchical networks have been proposed in the literature. This paper introduces a framework for classifying hierarchical topologies. Using the framework, we survey existing topologies in an organized fashion and identify the major design choices. We show how new hierarchical networks can be generated by varying architectural parameters in the framework. The performance evaluation of the numerous topologies remains a non-trivial task; we describe some preliminary efforts in that direction.
|Original language||English (US)|
|Title of host publication||Proceedings of the 1996 ICPP Workshop on Challenges for Parallel Processing, ICPPW 1996|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||10|
|State||Published - 1996|
|Event||1996 ICPP Workshop on Challenges for Parallel Processing, ICPPW 1996 - Ithaca, United States|
Duration: Aug 12 1996 → Aug 12 1996
|Name||Proceedings of the International Conference on Parallel Processing Workshops|
|Other||1996 ICPP Workshop on Challenges for Parallel Processing, ICPPW 1996|
|Period||8/12/96 → 8/12/96|
Bibliographical noteFunding Information:
This work was supported in part by the National Science Foundation under Grants No. US NSF MIP-8410110 and US NSF (hy89-20891, the US Department of Energy under Grant No. US DOE DE-FG02-85ER25001, the NASA Ames Research Center under Grant No. NASA NCC 2-559, Sun Microsystem, and an SFSU Faculty Research Affirmative Action Grant.
© 1996 IEEE.