Leakage reduction through optimization of regular layout parameters

Keyphrases

• Leakage Reduction 100%
• Layout Parameters 100%
• Regular Layout 100%
• Design Rules 50%
• Active Energy 50%
• Non-rectangular Gate 50%
• Leakage Current 25%
• Subwavelength 25%
• Technology Node 25%
• Circuit Performance 25%
• Optimization Techniques 25%
• Leakage Energy 25%
• Lithography 25%
• Induced Effect 25%
• CMOS Design 25%
• 65 Nm Technology 25%
• Layout Optimization 25%
• 32nm Technology 25%
• Energy Circuit 25%
• Physical Layout 25%

Engineering

• Design Rule 100%
• Nodes 50%
• Experimental Result 50%
• Circuit Performance 50%
• Lithography 50%
• Layout Optimization 50%
• Optimization Technique 50%

Material Science

• Electronic Circuit 100%
• Lithography 33%