Leakage power analysis and reduction for nanoscale circuits

Amit Agarwal, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy, Chris H. Kim

Research output: Contribution to journalArticlepeer-review

119 Scopus citations

Abstract

Leakage current in the nanometer regime has become a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickness scale downward. Various techniques are available to reduce leakage power in high-performance systems.

Original languageEnglish (US)
Pages (from-to)68-80
Number of pages13
JournalIEEE Micro
Volume26
Issue number2
DOIs
StatePublished - Mar 2006

Bibliographical note

Funding Information:
The research was funded in part by Semi conductor Research Corp. (SRC 1078.001), the Gigascale System Research Center, Intel, and IBM.

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