Leakage power analysis and reduction for nanoscale circuits

Amit Agarwal, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy, Chris H. Kim

Research output: Contribution to journalArticlepeer-review

105 Scopus citations


Leakage current in the nanometer regime has become a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickness scale downward. Various techniques are available to reduce leakage power in high-performance systems.

Original languageEnglish (US)
Pages (from-to)68-80
Number of pages13
JournalIEEE Micro
Issue number2
StatePublished - Mar 1 2006

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