Abstract
Leakage current in the nanometer regime has become a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickness scale downward. Various techniques are available to reduce leakage power in high-performance systems.
Original language | English (US) |
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Pages (from-to) | 68-80 |
Number of pages | 13 |
Journal | IEEE Micro |
Volume | 26 |
Issue number | 2 |
DOIs | |
State | Published - Mar 2006 |
Bibliographical note
Funding Information:The research was funded in part by Semi conductor Research Corp. (SRC 1078.001), the Gigascale System Research Center, Intel, and IBM.