Leakage power analysis and reduction for nanoscale circuits

Amit Agarwal; Saibal Mukhopadhyay; Arijit Raychowdhury; Kaushik Roy; Chris H. Kim

doi:10.1109/MM.2006.39

Leakage power analysis and reduction for nanoscale circuits

Amit Agarwal, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy, Chris H. Kim

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

105 Scopus citations

Abstract

Leakage current in the nanometer regime has become a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickness scale downward. Various techniques are available to reduce leakage power in high-performance systems.

Original language	English (US)
Pages (from-to)	68-80
Number of pages	13
Journal	IEEE Micro
Volume	26
Issue number	2
DOIs	https://doi.org/10.1109/MM.2006.39
State	Published - Mar 1 2006

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title = "Leakage power analysis and reduction for nanoscale circuits",

abstract = "Leakage current in the nanometer regime has become a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickness scale downward. Various techniques are available to reduce leakage power in high-performance systems.",

author = "Amit Agarwal and Saibal Mukhopadhyay and Arijit Raychowdhury and Kaushik Roy and Kim, {Chris H.}",

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AU - Mukhopadhyay, Saibal

AU - Raychowdhury, Arijit

AU - Roy, Kaushik

AU - Kim, Chris H.

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AB - Leakage current in the nanometer regime has become a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickness scale downward. Various techniques are available to reduce leakage power in high-performance systems.

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