Semiconductor devices are aggressively scaled each technology generation to achieve high integration density while the supply voltage is scaled to achieve lower switch ing energy per device. However, to achieve high performance there is need for commensurate scaling of the transistor threshold voltage (Vth). Scaling of transis tor threshold voltage is associated with exponential increase in subthreshold leakage current. Aggressive scaling of the devices in the nano-metre regime not only increases the subthreshold leakage but also has other negative impacts such as increased DIBL, VGh roll-off, reduced on-current to off-current ratio and increased source-drain resis tance. To avoid these short-channel effects, oxide thickness scaling and higher and non-uniform doping needs to be incorporated as the devices are scaled in nano metre regime, which results in exponential increase in gate and junction band-to-bandtunnelling leakage. This increase in total leakage causes the leakage current to become a major component of total power consumption. Hence, leakage reduction techniques are becoming indispensable in future designs. This chapter explained the various leak age mechanisms and discussed different circuit level techniques to reduce leakage energy and design tradeoffs.
|Original language||English (US)|
|Title of host publication||System-on-Chip|
|Subtitle of host publication||Next Generation Electronics|
|Publisher||Institution of Engineering and Technology|
|Number of pages||34|
|ISBN (Print)||0863415520, 9780863415524|
|State||Published - Jan 1 2006|