Despite the ubiquity of multicores, it is as important as ever to deliver high single-thread performance. An appealing way to accomplish this is by shutting down the idle cores in the chip and running the busy, performance-critical core(s) at higher-than-nominal frequencies. To enable such frequencies, two low-overhead approaches either boost voltage beyond nominal values, or pair cores in leader-checker con.gurations and let them run beyond safe frequency margins. We observe that, in a large multicore with varying numbers of busy cores, individual application of either of these two techniques is suboptimal. Each alone is often unable to bring the multicore all the way to its power or temperature envelopes due to limitations in supply voltage or error rate. Moreover, we show that the two techniques are complementary, and can be synergistically combined to unlock much higher levels of single-thread performance. Finally, we demonstrate a dynamic controller that optimizes the two techniques. Our data shows that, given a 16-core multicore where half of the cores are already busy, an additional, performance-critical thread now attains 34% higher performance than before, while consuming 220% more power.
|Original language||English (US)|
|Title of host publication||HPCA-16 2010 - The 16th International Symposium on High-Performance Computer Architecture|
|State||Published - May 27 2010|
|Event||16th International Symposium on High-Performance Computer Architecture, HPCA-16 2010 - Bangalore, India|
Duration: Jan 9 2010 → Jan 14 2010
|Other||16th International Symposium on High-Performance Computer Architecture, HPCA-16 2010|
|Period||1/9/10 → 1/14/10|