Layout optimization using arbitrarily high degree posynomial models

Piyush K. Sancheti, Sachin S. Sapatnekar

Research output: Contribution to journalArticlepeer-review

Abstract

The problem of designing individual macrocells for a library with power and speed considerations is addressed here. A new technique for optimization using posynomial [1] approximating functions is devised. In the design of each macrocell, optimality in design is critical and highly accurate techniques for measuring the performance are required during optimization. This paper presents methods for accurately estimating the worst-case contribution of the power and delay of a cell to a circuit. The program uses circuit-level simulation to calculate the power dissipation and delay of the cell with the highest accuracy. A rationale for using arbitrary degree posynomial modeling functions for area, delay and power modeling is presented. The problem is then formulated as a convex programming problem, and a rigorous optimization technique is used to arrive at the optimal macrocell.

Original languageEnglish (US)
Pages (from-to)53-56
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume1
StatePublished - Jan 1 1995

Fingerprint Dive into the research topics of 'Layout optimization using arbitrarily high degree posynomial models'. Together they form a unique fingerprint.

Cite this