Abstract
Recently, a low-latency decoding scheme called the simplified successive cancellation (SSC) algorithm has been proposed for polar codes. In this brief, we present the first systematic approach to formally derive the SSC decoding latency for any given polar code. The method to derive the SSC polar decoder architecture for any specific code is also presented. Moreover, the architecture of the precomputation SSC polar decoder is also proposed, which can further reduce the decoding latency. Compared with their SC decoder counterparts, the proposed SSC and precomputation SSC polar decoders can save up to 39.6% decoding latency with the same hardware cost.
| Original language | English (US) |
|---|---|
| Article number | 6680761 |
| Pages (from-to) | 115-119 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
| Volume | 61 |
| Issue number | 2 |
| DOIs | |
| State | Published - Jan 1 2014 |
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Keywords
- Binary tree
- Data-flow graph (DFG)
- Polar codes
- Precomputation
- Simplified successive cancellation (SSC)
Cite this
Latency analysis and architecture design of simplified SC polar decoders. / Zhang, Chuan; Parhi, Keshab K.
In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 61, No. 2, 6680761, 01.01.2014, p. 115-119.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Latency analysis and architecture design of simplified SC polar decoders
AU - Zhang, Chuan
AU - Parhi, Keshab K
PY - 2014/1/1
Y1 - 2014/1/1
N2 - Recently, a low-latency decoding scheme called the simplified successive cancellation (SSC) algorithm has been proposed for polar codes. In this brief, we present the first systematic approach to formally derive the SSC decoding latency for any given polar code. The method to derive the SSC polar decoder architecture for any specific code is also presented. Moreover, the architecture of the precomputation SSC polar decoder is also proposed, which can further reduce the decoding latency. Compared with their SC decoder counterparts, the proposed SSC and precomputation SSC polar decoders can save up to 39.6% decoding latency with the same hardware cost.
AB - Recently, a low-latency decoding scheme called the simplified successive cancellation (SSC) algorithm has been proposed for polar codes. In this brief, we present the first systematic approach to formally derive the SSC decoding latency for any given polar code. The method to derive the SSC polar decoder architecture for any specific code is also presented. Moreover, the architecture of the precomputation SSC polar decoder is also proposed, which can further reduce the decoding latency. Compared with their SC decoder counterparts, the proposed SSC and precomputation SSC polar decoders can save up to 39.6% decoding latency with the same hardware cost.
KW - Binary tree
KW - Data-flow graph (DFG)
KW - Polar codes
KW - Precomputation
KW - Simplified successive cancellation (SSC)
UR - http://www.scopus.com/inward/record.url?scp=84896743613&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84896743613&partnerID=8YFLogxK
U2 - 10.1109/TCSII.2013.2291065
DO - 10.1109/TCSII.2013.2291065
M3 - Article
AN - SCOPUS:84896743613
VL - 61
SP - 115
EP - 119
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
SN - 1549-8328
IS - 2
M1 - 6680761
ER -