Latency analysis and architecture design of simplified SC polar decoders

Chuan Zhang, Keshab K Parhi

Research output: Contribution to journalArticle

28 Citations (Scopus)

Abstract

Recently, a low-latency decoding scheme called the simplified successive cancellation (SSC) algorithm has been proposed for polar codes. In this brief, we present the first systematic approach to formally derive the SSC decoding latency for any given polar code. The method to derive the SSC polar decoder architecture for any specific code is also presented. Moreover, the architecture of the precomputation SSC polar decoder is also proposed, which can further reduce the decoding latency. Compared with their SC decoder counterparts, the proposed SSC and precomputation SSC polar decoders can save up to 39.6% decoding latency with the same hardware cost.

Original languageEnglish (US)
Article number6680761
Pages (from-to)115-119
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume61
Issue number2
DOIs
StatePublished - Jan 1 2014

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Decoding
Hardware
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Keywords

  • Binary tree
  • Data-flow graph (DFG)
  • Polar codes
  • Precomputation
  • Simplified successive cancellation (SSC)

Cite this

Latency analysis and architecture design of simplified SC polar decoders. / Zhang, Chuan; Parhi, Keshab K.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 61, No. 2, 6680761, 01.01.2014, p. 115-119.

Research output: Contribution to journalArticle

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