This paper presents the design of a K=3, 2Mbps Turbo decoder chip targeted for 3rd generation wideband CDMA (W-CDMA) systems. This paper makes two contributions. First, finite precision effects on the decoder performance are analyzed and optimal word-lengths are determined. Second, novel power-down techniques are proposed, with which very high power-down efficiency can be achieved without significant performance degradation. The decoder has been designed and fabricated using a 0.25μm standard cell library. The core size is 2.32mm×1.72mm and contains 300K transistors.
|Original language||English (US)|
|Number of pages||4|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|State||Published - Jan 1 2000|
|Event||CICC 2000: 22nd Annual Custom Integrated Circuits Conference - Orlando, FL, USA|
Duration: May 21 2000 → May 24 2000