K=3, 2Mbs low power turbo decoder for 3rd generation W-CDMA systems

Hiroshi Suzuki, Zhongfeng Wang, Keshab K. Parhi

Research output: Contribution to journalConference articlepeer-review

8 Scopus citations

Abstract

This paper presents the design of a K=3, 2Mbps Turbo decoder chip targeted for 3rd generation wideband CDMA (W-CDMA) systems. This paper makes two contributions. First, finite precision effects on the decoder performance are analyzed and optimal word-lengths are determined. Second, novel power-down techniques are proposed, with which very high power-down efficiency can be achieved without significant performance degradation. The decoder has been designed and fabricated using a 0.25μm standard cell library. The core size is 2.32mm×1.72mm and contains 300K transistors.

Original languageEnglish (US)
Pages (from-to)39-42
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
StatePublished - Jan 1 2000
EventCICC 2000: 22nd Annual Custom Integrated Circuits Conference - Orlando, FL, USA
Duration: May 21 2000May 24 2000

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