Abstract
A novel K-nested layered look-ahead method and its corresponding architectures, which pack K trellis steps into one step (where K is the encoder constraint length) and combine two look-ahead sub-trellises in a layered manner, are proposed for a high throughput Viterbi decoder. The proposed method guarantees parallel paths between any two-trellis states in the look-ahead trellises and distributes the add-compare-select computations to all trellis layers. It leads to a regular and simple architecture for the Viterbi decoding algorithm. The proposed method can be implemented in a partly or fully parallel manner and can be used for a high throughput Viterbi decoder. The main advantage of the proposed design is that it has the least latency among all look-ahead Viterbi decoders for a given level of parallelism.
| Original language | English (US) |
|---|---|
| Title of host publication | 2003 IEEE Workshop on Signal Processing Systems |
| Subtitle of host publication | Design and Implementation, SIPS 2003 |
| Editors | Wonyong Sung, Myung Hoon Sunwoo |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 99-104 |
| Number of pages | 6 |
| ISBN (Electronic) | 0780377958 |
| DOIs | |
| State | Published - 2003 |
| Event | 2003 IEEE Workshop on Signal Processing Systems, SIPS 2003 - Seoul, Korea, Republic of Duration: Aug 27 2003 → Aug 29 2003 |
Publication series
| Name | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation |
|---|---|
| Volume | 2003-January |
| ISSN (Print) | 1520-6130 |
Other
| Other | 2003 IEEE Workshop on Signal Processing Systems, SIPS 2003 |
|---|---|
| Country/Territory | Korea, Republic of |
| City | Seoul |
| Period | 8/27/03 → 8/29/03 |
Bibliographical note
Publisher Copyright:© 2003 IEEE.
Keywords
- Computer architecture
- Concurrent computing
- Delay
- Distributed computing
- Feedback loop
- Iterative decoding
- Parallel processing
- Pipeline processing
- Throughput
- Viterbi algorithm