Joint precision optimization and high level synthesis for approximate computing

Chaofan Li, Wei Luo, Sachin S. Sapatnekar, Jiang Hu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

63 Scopus citations

Abstract

Approximate computing has been recognized as an effective low power technique for applications with intrinsic error tolerance, such as image processing and machine learning. Existing efforts on this front are mostly focused on approximate circuit design, approximate logic synthesis or processor architecture approximation techniques. This work aims at how to make good use of approximate circuits at system and block level. In particular, approximation aware scheduling, functional unit allocation and binding algorithms are developed for data intensive applications. Simple yet credible error models, which are essential for precision control in the optimizations, are investigated. The algorithms are further extended to include bitwidth optimization in fixed point computations. Experimental results, including those from Verilog simulations, indicate that the proposed techniques facilitate desired energy savings under latency and accuracy constraints.

Original languageEnglish (US)
Title of host publication2015 52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781450335201
DOIs
StatePublished - Jul 24 2015
Event52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015 - San Francisco, United States
Duration: Jun 8 2015Jun 12 2015

Publication series

NameProceedings - Design Automation Conference
Volume2015-July
ISSN (Print)0738-100X

Other

Other52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015
CountryUnited States
CitySan Francisco
Period6/8/156/12/15

Keywords

  • High level synthesis
  • approximate computing

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