Gallager's Low-Density Parity-Check (LDPC) codes have recently received a lot of attention because of their excellent performance. The decoder hardware implementation is obviously one of the most crucial issues determining the extent of LDPC applications in the real world. The straightforward fully parallel decoder architecture usually incurs too high complexity for many practical purposes and should be transformed to a partly parallel realization. In this paper, we propose a joint code and decoder design approach to construct a class of (3, k)-regular LDPC codes which exactly fit to a partly parallel decoder implementation. The partly parallel decoder architecture is suitbale for efficient VLSI implementation and it has been shown that the jointly developed (3, k)-regular LDPC codes have very good performance.
|Original language||English (US)|
|Number of pages||5|
|Journal||Conference Record of the Asilomar Conference on Signals, Systems and Computers|
|State||Published - 2001|
|Event||35th Asilomar Conference on Signals, Systems and Computers - Pacific Grove, CA, United States|
Duration: Nov 4 2001 → Nov 7 2001