In this paper, we discuss the limitations of the existing clock jitter reduction techniques, and introduce ΔΣ sampling, which can reduce the jitter-induced sampling error significantly. We investigate various feedback configurations, and show that NRZ and RZ feedback techniques both improve the jitter shaping properties of the ΔΣ sampler. However, in order to benefit from the superior jitter shaping, a constant feedback pulsewidth is required. We propose a new clocking scheme, called correlated clocking to address the feedback pulsewidth variations. This technique utilizes the correlation between the rising and falling edges of the on-chip clocks to eliminate the feedback pulsewidth jitter. We show that a 1st -order ΔΣ sampler with correlated RZ feedback can achieve the same SJNR as a ΔΣ sampler with switched-capacitor feedback. We then expand our analysis to 2nd - and higher-order modulators, and show that contrary to common belief, even with constant-pulsewidth feedback, higher-order modulators are limited by the feedback pulse jitter. We conclude that the maximum benefit of a ΔΣ sampler with a conventional single-loop architecture is independent of the loop order, feedback mechanism, and the oversampling ratio, and it reaches 4.77 dB for OSR≥5.
|Original language||English (US)|
|Number of pages||11|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|State||Published - Jan 2020|
Bibliographical noteFunding Information:
Manuscript received April 19, 2019; revised July 29, 2019 and September 7, 2019; accepted September 24, 2019. Date of publication December 12, 2019; date of current version January 15, 2020. This work was supported by the DARPA CLASIC Program. This article was recommended by Associate Editor A. M. A. Ali. (Corresponding author: Shiva Jamali-Zavareh.) The authors are with the University of Minnesota, Twin cities, MN 55455 USA (e-mail: email@example.com).
- high speed
- jitter suppression