Issues and support for dynamic register allocation

Abhinav Das, Rao Fu, Antonia Zhai, Wei Chung Hsu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations


Post-link and dynamic optimizations have become important to achieve program performance. A major challenge in post-link and dynamic optimizations is the acquisition of registers for inserting optimization code in the main program. It is difficult to achieve both correctness and transparency when software-only schemes for acquiring registers are used, as described in [1]. We propose an architecture feature that builds upon existing hardware for stacked register allocation on the Itanium processor. The hardware impact of this feature is minimal, while simultaneously allowing post-link and dynamic optimization systems to obtain registers for optimization in a "safe" manner, thus preserving the transparency and improving the performance of these systems.

Original languageEnglish (US)
Title of host publicationAdvances in Computer Systems Architecture - 11th Asia-Pacific Conference, ACSAC 2006, Proceedings
PublisherSpringer Verlag
Number of pages8
ISBN (Print)3540400567, 9783540400561
StatePublished - 2006
Event11th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2006 - Shanghai, China
Duration: Sep 6 2006Sep 8 2006

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume4186 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


Other11th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2006


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