Over the years, there has been tremendous progress in developing new methods for modeling and diagnosing reliability at the level of individual transistors and interconnects. The thrust to propagate these models to higher levels of abstraction to predict the reliability of larger circuits is much more recent. This paper addresses the intersection of physics, circuits, and architecture for reliability modeling and optimization that must come together for cross-layer optimization. For various device reliability phenomena, this paper shows how physical models can be leveraged at the circuit level, or circuit models at the architecture level, to deliver composite solutions that comprehend chip-level design goals.
|Original language||English (US)|
|Title of host publication||Proceedings of the 53rd Annual Design Automation Conference, DAC 2016|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|State||Published - Jun 5 2016|
|Event||53rd Annual ACM IEEE Design Automation Conference, DAC 2016 - Austin, United States|
Duration: Jun 5 2016 → Jun 9 2016
|Name||Proceedings - Design Automation Conference|
|Other||53rd Annual ACM IEEE Design Automation Conference, DAC 2016|
|Period||6/5/16 → 6/9/16|
Bibliographical noteFunding Information:
This work was supported in part by NSF awards CCF-1017778 and CCF-1162267 and by SRC contract 2012-TJ-2234.
© 2016 ACM.
Copyright 2016 Elsevier B.V., All rights reserved.
- Bias temperature instability
- Cross-layer optimization
- Hot carriers
- Oxide breakdown