Invited - Optimizing device reliability effects at the intersection of physics, circuits, and architecture

Deepashree Sengupta; Vivek Mishra; Sachin S. Sapatnekar

doi:10.1145/2897937.2905016

Invited - Optimizing device reliability effects at the intersection of physics, circuits, and architecture

Deepashree Sengupta, Vivek Mishra, Sachin S. Sapatnekar

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Scopus citations

Abstract

Over the years, there has been tremendous progress in developing new methods for modeling and diagnosing reliability at the level of individual transistors and interconnects. The thrust to propagate these models to higher levels of abstraction to predict the reliability of larger circuits is much more recent. This paper addresses the intersection of physics, circuits, and architecture for reliability modeling and optimization that must come together for cross-layer optimization. For various device reliability phenomena, this paper shows how physical models can be leveraged at the circuit level, or circuit models at the architecture level, to deliver composite solutions that comprehend chip-level design goals.

Original language	English (US)
Title of host publication	Proceedings of the 53rd Annual Design Automation Conference, DAC 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781450342360
DOIs	https://doi.org/10.1145/2897937.2905016
State	Published - Jun 5 2016
Event	53rd Annual ACM IEEE Design Automation Conference, DAC 2016 - Austin, United States Duration: Jun 5 2016 → Jun 9 2016

Publication series

Name	Proceedings - Design Automation Conference
Volume	05-09-June-2016
ISSN (Print)	0738-100X

Other

Other	53rd Annual ACM IEEE Design Automation Conference, DAC 2016
Country/Territory	United States
City	Austin
Period	6/5/16 → 6/9/16

Bibliographical note

Publisher Copyright:
© 2016 ACM.

Keywords

Bias temperature instability
Cross-layer optimization
Electromigration
Hot carriers
Oxide breakdown
Reliability

Publisher link

10.1145/2897937.2905016

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Sengupta, D., Mishra, V., & Sapatnekar, S. S. (2016). Invited - Optimizing device reliability effects at the intersection of physics, circuits, and architecture. In Proceedings of the 53rd Annual Design Automation Conference, DAC 2016 Article a31 (Proceedings - Design Automation Conference; Vol. 05-09-June-2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/2897937.2905016

Invited - Optimizing device reliability effects at the intersection of physics, circuits, and architecture. / Sengupta, Deepashree; Mishra, Vivek; Sapatnekar, Sachin S.
Proceedings of the 53rd Annual Design Automation Conference, DAC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. a31 (Proceedings - Design Automation Conference; Vol. 05-09-June-2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sengupta, D, Mishra, V & Sapatnekar, SS 2016, Invited - Optimizing device reliability effects at the intersection of physics, circuits, and architecture. in Proceedings of the 53rd Annual Design Automation Conference, DAC 2016., a31, Proceedings - Design Automation Conference, vol. 05-09-June-2016, Institute of Electrical and Electronics Engineers Inc., 53rd Annual ACM IEEE Design Automation Conference, DAC 2016, Austin, United States, 6/5/16. https://doi.org/10.1145/2897937.2905016

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abstract = "Over the years, there has been tremendous progress in developing new methods for modeling and diagnosing reliability at the level of individual transistors and interconnects. The thrust to propagate these models to higher levels of abstraction to predict the reliability of larger circuits is much more recent. This paper addresses the intersection of physics, circuits, and architecture for reliability modeling and optimization that must come together for cross-layer optimization. For various device reliability phenomena, this paper shows how physical models can be leveraged at the circuit level, or circuit models at the architecture level, to deliver composite solutions that comprehend chip-level design goals.",

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Invited - Optimizing device reliability effects at the intersection of physics, circuits, and architecture

Abstract

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Keywords

Publisher link

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