This work presents measured test-data corresponding to a comprehensive reliability characterization of diode-connected MOS transistors. An array-based test structure, with the specific aim of quantifying the impact of feedback on the aging dynamics for the circuit configuration of interest was designed and implemented in a 65nm Low-Power (LP) process. Through detailed measurement data obtained using the test-vehicle we, (1) characterize the impact of feedback on the aging rate and compare it to the no-feedback case (2) evaluate the efficacy of iterative simulations for lifetime projection in such scenarios with the method based on the universality of hot carrier degradation extended to the case featuring feedback.
|Original language||English (US)|
|Title of host publication||2019 IEEE International Reliability Physics Symposium, IRPS 2019|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|State||Published - May 22 2019|
|Event||2019 IEEE International Reliability Physics Symposium, IRPS 2019 - Monterey, United States|
Duration: Mar 31 2019 → Apr 4 2019
|Name||IEEE International Reliability Physics Symposium Proceedings|
|Conference||2019 IEEE International Reliability Physics Symposium, IRPS 2019|
|Period||3/31/19 → 4/4/19|
Bibliographical noteFunding Information:
ACKNOWLEDGMENT This work was supported by in part by the Semiconductor Research Corporation (SRC) and the Texas Analog Center of Excellence (TxACE).
© 2019 IEEE.
- Analog / Mixed-Signal Aging
- Bond-dispersion model
- Circuit aging
- Circuit reliability
- Hot carrier injection (HCI)
- Lateral scaling
- Universality of degradation
- Voltage acceleration model