The increased demand for battery operated devices has placed added pressure on lowered supply voltages. Technology scaling proportionally scales supply voltages to maintain device reliability but threshold voltages have not scaled as rapidly to limit the off current leakage in transistors. Delta sigma ADCs, particularly, continuous time delta sigma modulator are attractive due to implicit anti-aliasing, relaxed speed requirements on the active elements and the use of resistive input impedances. Although the use of multibit quantizers relaxes the design of the loop filter and are less sensitive to clock jitter, single-bit designs are simpler and do not require any dynamic element matching. The design of first integrator in a single bit modulator with adequate linearity and low power is always a challenge particularly in lower technologies .
|Original language||English (US)|
|Title of host publication||Analog Circuits and Signal Processing|
|Number of pages||11|
|State||Published - 2017|
|Name||Analog Circuits and Signal Processing|
Bibliographical notePublisher Copyright:
© 2017, Springer International Publishing AG.
- Common Mode Rejection Ratio
- Common Mode Voltage
- Delta Sigma Modulator
- Gain Stage
- Harmonic Distortion