Interleaving buffer insertion and transistor sizing into a single optimization

Yanbin Jiang; Sachin S. Sapatnekar; Cyrus Bamji; Juho Kim

doi:10.1109/92.736136

Interleaving buffer insertion and transistor sizing into a single optimization

Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

30 Scopus citations

Abstract

This work presents strategies to insert buffers in a circuit, combined with gate sizing, to achieve better power-delay and area-delay tradeoffs. The purpose of this work is to examine how combining a sizing algorithm with buffer insertion will help us achieve better area-delay or power-delay tradeoffs, and to determine where and when to insert buffers in a circuit. The delay model incorporates placement-based information and the effect of input slew rates on gate delays. The results obtained by using the new method are significantly better than the results given by merely using a TILOS-like gate sizing algorithm alone, as is illustrated by several area-delay tradeoff curves shown in this paper.

Original language	English (US)
Pages (from-to)	625-633
Number of pages	9
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	6
Issue number	4
DOIs	https://doi.org/10.1109/92.736136
State	Published - 1998

Bibliographical note

Funding Information:
Manuscript received April 18, 1997; revised September 12, 1997. This work was supported in part by a grant from Cadence Design Systems, a DAC graduate scholarship, and the NSF under Grant MIP-9502556. Y. Jiang is with the Department of Electrical and Computer Engineering, Iowa State University, Ames, IA 50011 USA. S. S. Sapatnekar is with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA. C. Bamji is with Cadence Design Systems, San Jose, CA 95134 USA. J. Kim is with Sogang University, Seoul, South Korea. Publisher Item Identifier S 1063-8210(98)05988i-5.

Funding Information:
Dr. Sapatnekar has served as an Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: ANALOG AND DIGITAL SIGNAL PROCESSING, and has served on program committees for various conferences. He is a recipient of the NSF Career Award and Best Paper Awards at DAC-97 and ICCD-98.

Keywords

Buffer insertion
Elmore delay
Transistor sizing

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10.1109/92.736136

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title = "Interleaving buffer insertion and transistor sizing into a single optimization",

abstract = "This work presents strategies to insert buffers in a circuit, combined with gate sizing, to achieve better power-delay and area-delay tradeoffs. The purpose of this work is to examine how combining a sizing algorithm with buffer insertion will help us achieve better area-delay or power-delay tradeoffs, and to determine where and when to insert buffers in a circuit. The delay model incorporates placement-based information and the effect of input slew rates on gate delays. The results obtained by using the new method are significantly better than the results given by merely using a TILOS-like gate sizing algorithm alone, as is illustrated by several area-delay tradeoff curves shown in this paper.",

keywords = "Buffer insertion, Elmore delay, Transistor sizing",

author = "Yanbin Jiang and Sapatnekar, {Sachin S.} and Cyrus Bamji and Juho Kim",

note = "Funding Information: Manuscript received April 18, 1997; revised September 12, 1997. This work was supported in part by a grant from Cadence Design Systems, a DAC graduate scholarship, and the NSF under Grant MIP-9502556. Y. Jiang is with the Department of Electrical and Computer Engineering, Iowa State University, Ames, IA 50011 USA. S. S. Sapatnekar is with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA. C. Bamji is with Cadence Design Systems, San Jose, CA 95134 USA. J. Kim is with Sogang University, Seoul, South Korea. Publisher Item Identifier S 1063-8210(98)05988i-5. Funding Information: Dr. Sapatnekar has served as an Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: ANALOG AND DIGITAL SIGNAL PROCESSING, and has served on program committees for various conferences. He is a recipient of the NSF Career Award and Best Paper Awards at DAC-97 and ICCD-98.",

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N2 - This work presents strategies to insert buffers in a circuit, combined with gate sizing, to achieve better power-delay and area-delay tradeoffs. The purpose of this work is to examine how combining a sizing algorithm with buffer insertion will help us achieve better area-delay or power-delay tradeoffs, and to determine where and when to insert buffers in a circuit. The delay model incorporates placement-based information and the effect of input slew rates on gate delays. The results obtained by using the new method are significantly better than the results given by merely using a TILOS-like gate sizing algorithm alone, as is illustrated by several area-delay tradeoff curves shown in this paper.

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Interleaving buffer insertion and transistor sizing into a single optimization

Abstract

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