Interleaved successive cancellation polar decoders

Chuan Zhang, Keshab K. Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

Polar codes are among the most promising error correction codes due to their ability to achieve the symmetric capacities of the binary-input discrete memoryless channels (B-DMCs). However, how to design successive cancellation (SC) decoders which can maximize the hardware utilization efficiency is still challenging due to the inherent serial nature of SC decoding algorithm. To this end, in this paper, formal design approaches for designing both the time-constrained and resource-constrained interleaved SC decoders are proposed. Compared with the state-of-the-art design, the proposed interleaved decoders can achieve more than 50% reduction in term of area-time product.

Original languageEnglish (US)
Title of host publication2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages401-404
Number of pages4
ISBN (Print)9781479934324
DOIs
StatePublished - Jan 1 2014
Event2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia
Duration: Jun 1 2014Jun 5 2014

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

Other2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
CountryAustralia
CityMelbourne, VIC
Period6/1/146/5/14

Keywords

  • Polar codes
  • interleaved decoder
  • resource-constrained
  • successive cancellation
  • time-constrained

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