@inproceedings{11adadf9e22140f19186e9abdebf536e,
title = "Interconnects in the third dimension: Design challenges for 3D ICs",
abstract = "Despite generation upon generation of scaling, computer chips have until now remained essentially 2-dimensional. Improvements in on-chip wire delay and in the maximum number of I/O per chip have not been able to keep up with transistor performance growth; it has become steadily harder to hide the discrepancy. 3D chip technologies come in a number of flavors, but are expected to enable the extension of CMOS performance. Designing in three dimensions, however, forces the industry to look at formerly-two-dimensional integration issues quite differently, and requires the re-fitting of multiple existing EDA capabilities.",
keywords = "3D, Bandwidth, Chip-stack, Hierarchical memory, Interconnect, Latency, Silicon carrier, Through-wafer via",
author = "Kerry Bernstein and Paul Andry and Jerome Cann and Phil Emma and David Greenberg and Wilfried Haensch and Mike Ignatowski and Steve Koester and John Magerlein and Ruchir Puri and Albert Young",
year = "2007",
doi = "10.1109/DAC.2007.375227",
language = "English (US)",
isbn = "1595936270",
series = "Proceedings - Design Automation Conference",
pages = "562--567",
booktitle = "2007 44th ACM/IEEE Design Automation Conference, DAC'07",
note = "2007 44th ACM/IEEE Design Automation Conference, DAC'07 ; Conference date: 04-06-2007 Through 08-06-2007",
}