Interconnects in the third dimension: Design challenges for 3D ICs

Kerry Bernstein, Paul Andry, Jerome Cann, Phil Emma, David Greenberg, Wilfried Haensch, Mike Ignatowski, Steve Koester, John Magerlein, Ruchir Puri, Albert Young

Research output: Chapter in Book/Report/Conference proceedingConference contribution

114 Scopus citations

Abstract

Despite generation upon generation of scaling, computer chips have until now remained essentially 2-dimensional. Improvements in on-chip wire delay and in the maximum number of I/O per chip have not been able to keep up with transistor performance growth; it has become steadily harder to hide the discrepancy. 3D chip technologies come in a number of flavors, but are expected to enable the extension of CMOS performance. Designing in three dimensions, however, forces the industry to look at formerly-two-dimensional integration issues quite differently, and requires the re-fitting of multiple existing EDA capabilities.

Original languageEnglish (US)
Title of host publication2007 44th ACM/IEEE Design Automation Conference, DAC'07
Pages562-567
Number of pages6
DOIs
StatePublished - Aug 2 2007
Event2007 44th ACM/IEEE Design Automation Conference, DAC'07 - San Diego, CA, United States
Duration: Jun 4 2007Jun 8 2007

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Other

Other2007 44th ACM/IEEE Design Automation Conference, DAC'07
CountryUnited States
CitySan Diego, CA
Period6/4/076/8/07

Keywords

  • 3D
  • Bandwidth
  • Chip-stack
  • Hierarchical memory
  • Interconnect
  • Latency
  • Silicon carrier
  • Through-wafer via

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