Integrating parallelizing compilation technology and processor architecture for cost-effective concurrent multithreading

Keyphrases

• Parallelizing 100%
• Single chip 100%
• Data Dependency 100%
• Application Program 100%
• Processor Architecture 100%
• Technology Architecture 100%
• Transistor 50%
• Performance Improvement 50%
• Parallelization 50%
• Compiler 50%
• Instruction-level Parallelism 50%
• Execution Model 50%
• Compiler Optimization 50%
• Execution Time 50%
• Single Thread 50%
• Multithreaded Architectures 50%
• Thread-level Speculation 50%
• Control Dependency 50%
• Multiprocessor 50%
• Multiple Granularity 50%
• Superscalar Processor 50%
• Model Limit 50%
• Coarse-grained Parallelism 50%
• Runtime Checking 50%
• Parallel Compilation 50%
• Submarine pipeline 50%
• Parallel Hardware 50%

Computer Science

• Multithreading 100%
• Data-Dependences 100%
• single-chip 100%
• Application Program 100%
• Processor Architecture 100%
• Parallelism 50%
• Execution Model 50%
• Instruction-Level Parallelism 50%
• Compiler Optimization 50%
• Execution Time 50%
• Granularity 50%
• Superscalar Processor 50%
• Control Dependence 50%
• Single Program 50%
• Coarse-Grained Parallelism 50%
• Instruction Issue 50%
• Run-Time Checking 50%
• Deep Pipeline 50%
• Parallel Hardware 50%
• multi-processor 50%