TY - JOUR
T1 - Integrated algorithm for combined placement and libraryless technology mapping
AU - Jiang, Yanbin
AU - Sapatnekar, Sachin S.
PY - 1999/12/1
Y1 - 1999/12/1
N2 - This paper presents a new solution for combining technology mapping with placement, coupling the two into one phase. The original aspects of our work are the use of libraryless mapping and a state space search mechanism that is used to find the best solution. Several heuristics are presented for speeding up the search. Comparisons with a more conventional approach show that these strategies provide improvements of about 20%, with reasonable CPU times, on benchmark circuits.
AB - This paper presents a new solution for combining technology mapping with placement, coupling the two into one phase. The original aspects of our work are the use of libraryless mapping and a state space search mechanism that is used to find the best solution. Several heuristics are presented for speeding up the search. Comparisons with a more conventional approach show that these strategies provide improvements of about 20%, with reasonable CPU times, on benchmark circuits.
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M3 - Conference article
AN - SCOPUS:0033346501
SN - 1092-3152
SP - 102
EP - 105
JO - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
JF - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
T2 - Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design (ICCAD-99)
Y2 - 7 November 1999 through 11 November 1999
ER -