Integral Sampler and Polynomial Multiplication Architecture for Lattice-based Cryptography

Antian Wang, Weihang Tan, Keshab K. Parhi, Yingjie Lao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

With the surge of the powerful quantum computer, lattice-based cryptography proliferated the latest cryptography hardware implementation due to its resistance against quantum computers. Among the computational blocks of lattice-based cryptography, the random errors produced by the sampler play a key role in ensuring the security of these schemes. This paper proposes an integral architecture for the sampler, which can reduce the overall resource consumption by reusing the multipliers and adders within the modular polynomial computation. For instance, our experimental results show that the proposed design can effectively reduce the discrete Ziggurat sampling method in DSP usage.

Original languageEnglish (US)
Title of host publicationProceedings - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022
EditorsLuca Cassano, Sreejit Chakravarty, Alberto Bosio
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665459389
DOIs
StatePublished - 2022
Event35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022 - Austin, United States
Duration: Oct 19 2022Oct 21 2022

Publication series

NameProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT
Volume2022-October
ISSN (Print)2576-1501
ISSN (Electronic)2765-933X

Conference

Conference35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022
Country/TerritoryUnited States
CityAustin
Period10/19/2210/21/22

Bibliographical note

Publisher Copyright:
© 2022 IEEE.

Keywords

  • Discrete Gaussian Sampling
  • Lattice-Based Cryptography
  • Post-Quantum Cryptography

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