For BSIT, it is well-known that the ideal relation between the drain current and the drain voltage with respect to the source is pentode-like, the saturated property. But the result from practical measurement shows ID increases slightly with the VD rising, just like the phenomenon observed in BJT, which is affected by `Base Width Modulation'. Authors induce that the main cause of it is `Gate-biasing Effect'. In this article, the effect is discussed in detail.
|Original language||English (US)|
|Number of pages||3|
|State||Published - Dec 1 1998|
|Event||Proceedings of the 1998 5th International Conference on Solid-State and Integrated Circuit Technology - Beijing, China|
Duration: Oct 21 1998 → Oct 23 1998
|Other||Proceedings of the 1998 5th International Conference on Solid-State and Integrated Circuit Technology|
|Period||10/21/98 → 10/23/98|