Tunneling field-effect transistors (TFETs) are of tremendous interest for advanced logic applications due to their potential for sub-60-mV/dec subthreshold slope which could enable supply voltage scaling beyond what is practical for conventional MOSFETs. However, TFETs based upon tunneling in Si suffer from low on current, ION, and fail to provide steep slope at high current levels. III-V TFETs are more promising due to their potential for high drive current, but the poor gate oxide quality remains a significant challenge. Recently, a hybrid III-V-on-Si approach  has been proposed as a potential solution to this problem, whereby the small effective band gap, E geff, of the InAs/Si heterojunction could increase ION, while preserving the high-quality Si/dielectric interface in the channel. Experimental demonstrations of nanostructured InAs-on-Si Esaki diodes and TFETs suggest this approach is feasible ,. However, InAs-on-Si heterostructures still exhibit relatively large Egeff (∼ 0.4 eV in unconfined geometries) and quantum effects increase Egeff substantially in confined geometries. In this paper, we provide a simulation analysis of a new device structure, the InAs/SiGe/Si TFET that could overcome this problem by utilizing a compressivelystrained SiGe layer to further decrease E geff. We show that ION in these devices increases by 5× (at constant Ioff) and further explore the various trade-offs and performance-limiting factors in these devices.